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? 2011-2014 microchip technology inc. ds70000652f-page 1 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 operating conditions ? 3.0v to 3.6v, -40 c to +125 c, dc to 16 mips ? 3.0v to 3.6v, -40 c to +150 c, dc to 5 mips core: 16-bit dspic33f cpu ? code-efficient (c and assembly) architecture ? two 40-bit wide accumulators ? single-cycle (mac/mpy) with dual data fetch ? single-cycle mixed-sign mul plus hardware divide ? 32-bit multiply support clock management ? 0.25% internal oscillator ? programmable plls and oscillator clock sources ? fail-safe clock monitor (fscm) ? independent watchdog timer (wdt) ? fast wake-up and start-up power management ? low-power management modes (sleep, idle, doze) ? integrated power-on reset and brown-out reset ? 1 ma/mhz dynamic current (typical) ?30 a i pd current (typical) pwm ? up to three pwm pairs ? two dead-time generators ? 31.25 ns pwm resolution ? pwm support for: - inverters, pfc, ups - bldc, pmsm, acim, srm ? class b-compliant fault inputs ? possibility of adc synchronization with pwm signal advanced analog features ? adc module: - 10-bit, 1.1 msps with four s&h - four analog inputs on 18-pin devices and up to 14 analog inputs on 44-pin devices ? flexible and independent adc trigger sources ? three comparator modules ? charge time measurement unit (ctmu): - supports mtouch? capacitive touch sensing - provides high-resolution time measurement (1 ns) - on-chip temperature measurement timers/output compare/input capture ? up to five general purpose timers: - one 16-bit and up to two 32-bit timers/counters ? two output compare modules ? three input capture modules ? peripheral pin select (pps) to allow function remap communication interfaces ? uart module (4 mbps): - with support for lin/j2602 protocols and irda ? ? 4-wire spi module (8 mhz maximum speed): - remappable pins in 32-kbyte flash devices ?i 2 c? module (400 khz) input/output ? sink/source 10 ma or 6 ma, pin-specific for standard v oh /v ol , up to 16 ma or 12 ma for non-standard v oh 1 ? 5v tolerant pins ? up to 20 selectable open-drain and pull-ups ? three external interrupts (two are remappable) qualification and class b support ? aec-q100 rev g (grade 0 -40 c to +150 c) ? class b safety library, iec 60730, ude certified debugger development support ? in-circuit and in-application programming ? up to three complex data breakpoints ? trace and run-time watch 16-bit digital signal controllers (up to 32-kbyte flash and 2-kbyte sram)
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 2 ? 2011-2014 microchip technology inc. dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 product families the device names, pin counts, memory sizes and peripheral availability of each device are listed in table 1 . the following pages show their pinout diagrams. table 1: dspic33fj16(gp/mc) 101/102 device features device pins program flash (kbyte) ram (kbytes) remappable peripherals motor control pwm pwm faults 10-bit, 1.1 msps adc rtcc i 2 c? comparators ctmu i/o pins packages remappable pins 16-bit timer ( 1 , 2 ) input capture output compare uart external interrupts ( 3 ) spi dspic33fj16gp101 18 16 1 8 3 3 2 1 3 1 ? ? 1 adc, 4-ch y1 3 y13pdip, soic 20 16 1 8 3 3 2 1 3 1 ? ? 1 adc, 4-ch y1 3 y15ssop dspic33fj16gp102 28 16 1 16 3 3 2 1 3 1 ? ? 1 adc, 6-ch y1 3 y21spdip, soic, ssop, qfn 36 16 1 16 3 3 2 1 3 1 ? ? 1 adc, 6-ch y 1 3 y 21 vtla dspic33fj16mc101 20 16 1 10 3 3 2 1 3 1 6-ch 1 1 adc, 4-ch y1 3 y15pdip, soic, ssop dspic33fj16mc102 28 16 1 16 3 3 2 1 3 1 6-ch 2 1 adc, 6-ch y1 3 y21spdip, soic, ssop, qfn 36 16 1 16 3 3 2 1 3 1 6-ch 2 1 adc, 6-ch y 1 3 y 21 vtla note 1: two out of three timers are remappable. 2: one pair can be combined to create one 32-bit timer. 3: two out of three interrupts are remappable.
? 2011-2014 microchip technology inc. ds70000652f-page 3 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 2: dspic33fj32(gp/mc)101 /102/104 device features device pins program flash (kbyte) ram (kbytes) remappable peripherals motor control pwm pwm faults 10-bit, 1.1 msps adc rtcc i 2 c? comparators ctmu i/o pins packages remappable pins 16-bit timer ( 1 , 2 ) input capture output compare uart external interrupts ( 3 ) spi dspic33fj32gp101 18 32 2 8 5 3 2 1 3 1 ? ? 1 adc, 6-ch y1 3 y13pdip, soic 20 32 2 8 5 3 2 1 3 1 ? ? 1 adc, 6-ch y1 3 y15ssop dspic33fj32gp102 28 32 2 16 5 3 2 1 3 1 ? ? 1 adc, 8-ch y1 3 y21spdip, soic, ssop, qfn 36 32 2 16 5 3 2 1 3 1 ? ? 1 adc, 8-ch y 1 3 y 21 vtla dspic33fj32gp104 44 32 2 26 5 3 2 1 3 1 ? ? 1 adc, 14-ch y 1 3 y 35 tqfp, qfn, vtla dspic33fj32mc101 20 32 2 10 5 3 2 1 3 1 6-ch 1 1 adc, 6-ch y1 3 y15pdip, soic, ssop DSPIC33FJ32MC102 28 32 2 16 5 3 2 1 3 1 6-ch 2 1 adc, 8-ch y1 3 y21spdip, soic, ssop, qfn 36 32 2 16 5 3 2 1 3 1 6-ch 2 1 adc, 8-ch y 1 3 y 21 vtla dspic33fj32mc104 44 32 2 26 5 3 2 1 3 1 6-ch 2 1 adc, 14-ch y 1 3 y 35 tqfp, qfn, vtla note 1: four out of five timers are remappable. 2: two pairs can be combined to have up to two 32-bit timers. 3: two out of three interrupts are remappable.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 4 ? 2011-2014 microchip technology inc. pin diagrams 18-pin pdip/soic dspic33fj16gp101 mclr pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 v dd v ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 sck1/int0/rp7 (1) /cn23/rb7 pgec3/sosco/t1ck/cn0/ra4 pged3/sosci/rp4 (1) /cn1/rb4 v cap osco/clko/cn29/ra3 osci/clki/cn30/ra2 v ss sda1/sdi1/rp9 (1) /cn21/rb9 scl1/sdo1/rp8 (1) /cn22/rb8 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 rp15 (1) /cn11/rb15 rtcc/rp14 (1) /cn12/rb14 note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. = pins are up to 5v tolerant dspic33fj32gp101 mclr pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 v dd v ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 int0/rp7 (1) /cn23/rb7 pgec3/sosco/an10/t1ck/cn0/ra4 pged3/sosci/an9/rp4 (1) /cn1/rb4 v cap osco/clko/cn29/ra3 osci/clki/cn30/ra2 v ss sda1/rp9 (1) /cn21/rb9 scl1/rp8 (1) /cn22/rb8 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 rp15 (1) /cn11/rb15 rtcc/rp14 (1) /cn12/rb14
? 2011-2014 microchip technology inc. ds70000652f-page 5 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 pin diagrams (continued) dspic33fj16gp101 mclr v ss pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 av dd av ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 sck1/int0/rp7 (1) /cn23/rb7 pgec3/sosco/t1ck/cn0/ra4 pged3/sosci/rp4 (1) /cn1/rb4 v cap osco/clko/cn29/ra3 osci/clki/cn30/ra2 v ss sda1/sdi1/rp9 (1) /cn21/rb9 scl1/sdo1/rp8 (1) /cn22/rb8 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 rp15 (1) /cn11/rb15 rtcc/rp14 (1) /cn12/rb14 v dd 20-pin ssop note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. = pins are up to 5v tolerant dspic33fj32gp101 mclr v ss pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 av dd av ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 int0/rp7 (1) /cn23/rb7 pgec3/sosco/an10/t1ck/cn0/ra4 pged3/sosci/an9/rp4 (1) /cn1/rb4 v cap osco/clko/cn29/ra3 osci/clki/cn30/ra2 v ss sda1/rp9 (1) /cn21/rb9 scl1/rp8 (1) /cn22/rb8 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 rp15 (1) /cn11/rb15 rtcc/rp14 (1) /cn12/rb14 v dd
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 6 ? 2011-2014 microchip technology inc. pin diagrams (continued) dspic33fj16gp102 mclr v ss v dd pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 av dd av ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 ascl1/rp6 (1) /cn24/rb6 pgec3/sosco/t1ck/cn0/ra4 pged3/sosci/rp4 (1) /cn1/rb4 v ss osco/clko/cn29/ra3 osci/clki/cn30/ra2 v cap sck1/int0/rp7 (1) /cn23/rb7 sda1/sdi1/rp9 (1) /cn21/rb9 scl1/sdo1/rp8 (1) /cn22/rb8 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 rp15 (1) /cn11/rb15 rtcc/rp14 (1) /cn12/rb14 rp13 (1) /cn13/rb13 rp12 (1) /cn14/rb12 rp10 (1) /cn16/rb10 rp11 (1) /cn15/rb11 asda1/rp5 (1) /cn27/rb5 28-pin spdip/soic/ssop note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. = pins are up to 5v tolerant dspic33fj32gp102 mclr v ss v dd pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 av dd av ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 ascl1/rp6 (1) /cn24/rb6 pgec3/sosco/an10/t1ck/cn0/ra4 pged3/sosci/an9/rp4 (1) /cn1/rb4 v ss osco/clko/cn29/ra3 osci/clki/cn30/ra2 v cap int0/rp7 (1) /cn23/rb7 sda1/rp9 (1) /cn21/rb9 scl1/rp8 (1) /cn22/rb8 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 rp15 (1) /cn11/rb15 rtcc/rp14 (1) /cn12/rb14 rp13 (1) /cn13/rb13 rp12 (1) /cn14/rb12 rp10 (1) /cn16/rb10 rp11 (1) /cn15/rb11 asda1/rp5 (1) /cn27/rb5
? 2011-2014 microchip technology inc. ds70000652f-page 7 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 pin diagrams (continued) dspic33fj16mc101 mclr v ss pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 v dd v ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 flta1 (2) /sck1/int0/rp7 (1) /cn23/rb7 pgec3/sosco/t1ck/cn0/ra4 pged3/sosci/rp4 (1) /cn1/rb4 pwm1h2/rp12 (1) /cn14/rb12 osco/clko/cn29/ra3 osci/clki/cn30/ra2 v cap sda1/sdi1/pwm1l3/rp9 (1) /cn21/rb9 scl1/sdo1/pwm1h3/rp8 (1) /cn22/rb8 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 pwm1l1/rp15 (1) /cn11/rb15 pwm1h1/rtcc/rp14 (1) /cn12/rb14 pwm1l2/rp13 (1) /cn13/rb13 20-pin pdip/soic/ssop note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the pwm fault pins are enabled and asserted during any reset event. refer to section 15.2 ?pwm faults? for more information on the pwm faults. = pins are up to 5v tolerant dspic33fj32mc101 mclr v ss pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 v dd v ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 flta1 (2) /int0/rp7 (1) /cn23/rb7 pgec3/sosco/an10/t1ck/cn0/ra4 pged3/sosci/an9/rp4 (1) /cn1/rb4 pwm1h2/rp12 (1) /cn14/rb12 osco/clko/cn29/ra3 osci/clki/cn30/ra2 v cap sda1/pwm1l3/rp9 (1) /cn21/rb9 scl1/pwm1h3/rp8 (1) /cn22/rb8 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 pwm1l1/rp15 (1) /cn11/rb15 pwm1h1/rtcc/rp14 (1) /cn12/rb14 pwm1l2/rp13 (1) /cn13/rb13
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 8 ? 2011-2014 microchip technology inc. pin diagrams (continued) note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the pwm fault pins are enabled and asserted during any reset event. refer to section 15.2 ?pwm faults? for more information on the pwm faults. dspic33fj16mc102 mclr v ss v dd pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 av dd av ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 flta1 (2) /ascl1/rp6 (1) /cn24/rb6 pgec3/sosco/t1ck/cn0/ra4 pged3/sosci/rp4 (1) /cn1/rb4 v ss osco/clko/cn29/ra3 osci/clki/cn30/ra2 v cap sck1/int0/rp7 (1) /cn23/rb7 sda1/sdi1/rp9 (1) /cn21/rb9 scl1/sdo1/rp8 (1) /cn22/rb8 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pwm1l1/rp15 (1) /cn11/rb15 pwm1h1/rtcc/rp14 (1) /cn12/rb14 pwm1l2/rp13 (1) /cn13/rb13 pwm1h2/rp12 (1) /cn14/rb12 pwm1h3/rp10 (1) /cn16/rb10 pwm1l3/rp11 (1) /cn15/rb11 fltb1 (2) /asda1/rp5 (1) /cn27/rb5 28-pin spdip/soic/ssop = pins are up to 5v tolerant DSPIC33FJ32MC102 mclr v ss v dd pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 av dd av ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 flta1 (2) /ascl1/rp6 (1) /cn24/rb6 pgec3/sosco/an10/t1ck/cn0/ra4 pged3/sosci/an9/rp4 (1) /cn1/rb4 v ss osco/clko/cn29/ra3 osci/clki/cn30/ra2 v cap int0/rp7 (1) /cn23/rb7 sda1/rp9 (1) /cn21/rb9 scl1/rp8 (1) /cn22/rb8 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pwm1l1/rp15 (1) /cn11/rb15 pwm1h1/rtcc/rp14 (1) /cn12/rb14 pwm1l2/rp13 (1) /cn13/rb13 pwm1h2/rp12 (1) /cn14/rb12 pwm1h3/rp10 (1) /cn16/rb10 pwm1l3/rp11 (1) /cn15/rb11 fltb1 (2) /asda1/rp5 (1) /cn27/rb5
? 2011-2014 microchip technology inc. ds70000652f-page 9 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 pin diagrams (continued) 28-pin qfn (2) note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. = pins are up to 5v tolerant 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 dspic33fj16gp102 5 4 mclr pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 v ss v cap sda1/sdi1/rp9 (1) /cn21/rb9 rp13 (1) /cn13/rb13 rp12 (1) /cn14/rb12 rp10 (1) /cn16/rb10 rp11 (1) /cn15/rb11 v ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 osco/clko/cn29/ra3 osci/clki/cn30/ra2 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 v dd pgec3/sosco/t1ck/cn0/ra4 asda1/rp5 (1) /cn27/rb5 pged3/sosci/rp4 (1) /cn1/rb4 ascl1/rp6 (1) /cn24/rb6 sck1/int0/rp7 (1) /cn23/rb7 scl1/sdo1/rp8 (1) /cn22/rb8 av dd av ss rp15 (1) /cn11/rb15 rtcc/rp14 (1) /cn12/rb14
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 10 ? 2011-2014 microchip technology inc. pin diagrams (continued) 28-pin qfn (2) note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal pad at the bottom of the device is not c onnected to any pins and is recommended to be connected to v ss externally. = pins are up to 5v tolerant 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 dspic33fj32gp102 5 4 mclr pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 v ss v cap sda1/rp9 (1) /cn21/rb9 rp13 (1) /cn13/rb13 rp12 (1) /cn14/rb12 rp10 (1) /cn16/rb10 rp11 (1) /cn15/rb11 v ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 osco/clko/cn29/ra3 osci/clki/cn30/ra2 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 v dd pgec3/soscoan10//t1ck/cn0/ra4 asda1/rp5 (1) /cn27/rb5 pged3/sosci/an9/rp4 (1) /cn1/rb4 ascl1/rp6 (1) /cn24/rb6 int0/rp7 (1) /cn23/rb7 scl1/rp8 (1) /cn22/rb8 av dd av ss rp15 (1) /cn11/rb15 rtcc/rp14 (1) /cn12/rb14
? 2011-2014 microchip technology inc. ds70000652f-page 11 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 pin diagrams (continued) 28-pin qfn (2) note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal pad at the bottom of the device is not c onnected to any pins and is recommended to be connected to v ss externally. 3: the pwm fault pins are enabled and asserted during any reset event. refer to section 15.2 ?pwm faults? for more information on the pwm faults. 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 dspic33fj16mc102 5 4 mclr pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 v ss v cap sda1/sdi1/rp9 (1) /cn21/rb9 pwm1l2/rp13 (1) /cn13/rb13 pwm1h2/rp12 (1) /cn14/rb12 pwm1h3/rp10 (1) /cn16/rb10 pwm1l3/rp11 (1) /cn15/rb11 v ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 osco/clko/cn29/ra3 osci/clki/cn30/ra2 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 v dd pgec3/sosco/t1ck/cn0/ra4 fltb1 (3) /asda1/rp5 (1) /cn27/rb5 pged3/sosci/rp4 (1) /cn1/rb4 flta1 (3) /ascl1/rp6 (1) /cn24/rb6 sck1/int0/rp7 (1) /cn23/rb7 scl1/sdo1/rp8 (1) /cn22/rb8 av dd av ss pwm1l1/rp15 (1) /cn11/rb15 pwm1h1/rtcc/rp14 (1) /cn12/rb14 = pins are up to 5v tolerant
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 12 ? 2011-2014 microchip technology inc. pin diagrams (continued) 28-pin qfn (2) note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. 3: the pwm fault pins are enabled and asserted during any reset event. refer to section 15.2 ?pwm faults? for more information on the pwm faults. 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 DSPIC33FJ32MC102 5 4 mclr pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 v ss v cap sda1/rp9 (1) /cn21/rb9 pwm1l2/rp13 (1) /cn13/rb13 pwm1h2/rp12 (1) /cn14/rb12 pwm1h3/rp10 (1) /cn16/rb10 pwm1l3/rp11 (1) /cn15/rb11 v ss pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 osco/clko/cn29/ra3 osci/clki/cn30/ra2 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 v dd pgec3/sosco/an10/t1ck/cn0/ra4 fltb1 (3) /asda1/rp5 (1) /cn27/rb5 pged3/sosci/an9/rp4 (1) /cn1/rb4 flta1 (3) /ascl1/rp6 (1) /cn24/rb6 int0/rp7 (1) /cn23/rb7 scl1/rp8 (1) /cn22/rb8 av dd av ss pwm1l1/rp15 (1) /cn11/rb15 pwm1h1/rtcc/rp14 (1) /cn12/rb14 = pins are up to 5v tolerant
? 2011-2014 microchip technology inc. ds70000652f-page 13 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 pin diagrams (continued) 36-pin vtla (2) note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. 1 dspic33fj16gp102 10 33 32 31 30 29 28 2 3 4 5 6 24 23 22 21 20 19 11 12 13 14 15 n/c pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 mclr av dd rp15 (1) /cn11/rb15 rtcc/rp14 (1) /cn12/rb14 av ss n/c n/c v ss sda1/sdi1/rp9 (1) /cn21/rb9 rp13 (1) /cn13/rb13 rp12 (1) /cn14/rb12 rp10 (1) /cn16/rb10 rp11 (1) /cn15/rb11 v dd v cap v dd pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 pged3/sosci/rp4 (1) /cn1/rb4 osco/clko/cn29/ra3 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 v ss osci/clki/cn30/ra2 n/c (vss) n/c asda1/rp5 (1) /cn27/rb5 pgec3/sosco/t1ck/cn0/ra4 ascl1/rp6 (1) /cn24/rb6 sck1/int0/rp7 (1) /cn23/rb7 scl1/sdo1/rp8 (1) /cn22/rb8 v dd n/c (v dd ) 7 8 9 34 35 36 16 17 18 27 26 25 = pins are up to 5v tolerant
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 14 ? 2011-2014 microchip technology inc. pin diagrams (continued) 36-pin vtla (2) note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal pad at the bottom of the device is not connec ted to any pins and is recommended to be connected to v ss externally. 1 dspic33fj32gp102 10 33 32 31 30 29 28 2 3 4 5 6 24 23 22 21 20 19 11 12 13 14 15 n/c pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 mclr av dd rp15 (1) /cn11/rb15 rtcc/rp14 (1) /cn12/rb14 av ss n/c n/c v ss sda1/rp9 (1) /cn21/rb9 rp13 (1) /cn13/rb13 rp12 (1) /cn14/rb12 rp10 (1) /cn16/rb10 rp11 (1) /cn15/rb11 v dd v cap v dd pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 pged3/sosci/an9/rp4 (1) /cn1/rb4 osco/clko/cn29/ra3 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 v ss osci/clki/cn30/ra2 n/c (vss) n/c asda1/rp5 (1) /cn27/rb5 pgec3/sosco/an10/t1ck/cn0/ra4 ascl1/rp6 (1) /cn24/rb6 int0/rp7 (1) /cn23/rb7 scl1/rp8 (1) /cn22/rb8 v dd n/c (v dd ) 7 8 9 34 35 36 16 17 18 27 26 25 = pins are up to 5v tolerant
? 2011-2014 microchip technology inc. ds70000652f-page 15 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 pin diagrams (continued) 36-pin vtla (2) note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal pad at the bottom of the device is not connec ted to any pins and is recommended to be connected to v ss externally. 3: the pwm fault pins are enabled and asserted during any reset event. refer to section 15.2 ?pwm faults? for more information on the pwm faults. n/c pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 mclr av dd pwm1l1/rp15 (1) /cn11/rb15 av ss n/c n/c v ss sda1/sdi1/rp9 (1) /cn21/rb9 pwm1l2/rp13 (1) /cn13/rb13 pwm1h2/rp12 (1) /cn14/rb12 pwm1h3/rp10 (1) /cn16/rb10 pwm1l3/rp11 (1) /cn15/rb11 v dd v cap v dd pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 pged3/sosci/rp4 (1) /cn1/rb4 osco/clko/cn29/ra3 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 v ss osci/clki/cn30/ra2 n/c (vss) n/c fltb1 (3) /asda1/rp5 (1) /cn27/rb5 pgec3/sosco/t1ck/cn0/ra4 flta1 (3) /ascl1/rp6 (1) /cn24/rb6 sck1/int0/rp7 (1) /cn23/rb7 scl1/sdo1/rp8 (1) /cn22/rb8 v dd n/c (v dd ) dspic33fj16mc102 = pins are up to 5v tolerant 1 10 33 32 31 30 29 28 2 3 4 5 6 24 23 22 21 20 19 11 12 13 14 15 7 8 9 34 35 36 16 17 18 27 26 25 pwm1h1/rtcc/rp14 (1) /cn12/rb14
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 16 ? 2011-2014 microchip technology inc. pin diagrams (continued) 36-pin vtla (2) note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. 3: the pwm fault pins are enabled and assert ed during any reset event. refer to section 15.2 ?pwm faults? for more information on the pwm faults. n/c pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 mclr av dd pwm1l1/rp15 (1) /cn11/rb15 pwm1h1/rtcc/rp14 (1) /cn12/rb14 av ss n/c n/c v ss sda1/rp9 (1) /cn21/rb9 pwm1l2/rp13 (1) /cn13/rb13 pwm1h2/rp12 (1) /cn14/rb12 pwm1h3/rp10 (1) /cn16/rb10 pwm1l3/rp11 (1) /cn15/rb11 v dd v cap v dd pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 pged3/sosci/an9/rp4 (1) /cn1/rb4 osco/clko/cn29/ra3 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 v ss osci/clki/cn30/ra2 n/c (vss) n/c fltb1 (3) /asda1/rp5 (1) /cn27/rb5 pgec3/sosco/an10/t1ck/cn0/ra4 flta1 (3) /ascl1/rp6 (1) /cn24/rb6 int0/rp7 (1) /cn23/rb7 scl1/rp8 (1) /cn22/rb8 v dd n/c (v dd ) DSPIC33FJ32MC102 = pins are up to 5v tolerant 1 10 33 32 31 30 29 28 2 3 4 5 6 24 23 22 21 20 19 11 12 13 14 15 7 8 9 34 35 36 16 17 18 27 26 25
? 2011-2014 microchip technology inc. ds70000652f-page 17 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 pin diagrams (continued) 44 43 42 41 40 39 38 37 36 35 34 133 232 331 430 529 628 727 826 925 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 44-pin tqfp = pins are up to 5v tolerant scl1/rp8 (1) /cn22/rb8 ra10 ra7 rtcc/rp14 (1) /cn12/rb14 rp15 (1) /cn11/rb15 a vss a vdd mclr pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 int0/rp7 (1) /cn23/rb7 ascl1/rp6 (1) /cn24/rb6 asda1/rp5 (1) /cn27/rb5 v dd v ss an15/rp21 (1) /cn26/rc5 an12/rp20 (1) /cn25/rc4 an11/rp19 (1) /cn28/rc3 ra9 pgec3/sosco/an10/t1ck/cn0/ra4 dspic33fj32gp104 rp13 (1) /cn13/rb13 rp12 (1) /cn14/rb12 rp11 (1) /cn15/rb11 rp10/cn16/rb10 v cap v ss rp25 (1) /cn19/rc9 rp24 (1) /cn20/rc8 rp23 (1) /cn17/rc7 sda1/rp9 (1) /cn21/rb9 rp22 (1) /cn18/rc6 peged3/sosci/an9/rp4 (1) /cn1/rb4 ra8 osc2/clk0/cn29/ra3 osc1/clki/cn30/ra2 v ss v dd an8/rp18 (1) /cn10/rc2 an7/rp17 (1) /cn9/rc1 an6/rp16 (1) /cn8/rc0 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 18 ? 2011-2014 microchip technology inc. pin diagrams (continued) 44-pin tqfp = pins are up to 5v tolerant 44 43 42 41 40 39 38 37 36 35 34 133 232 331 430 529 628 727 826 925 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 scl1/rp8 (1) /cn22/rb8 ra10 ra7 pwm1h1/rtcc/rp14 (1) /cn12/rb14 pwm1l1/rp15 (1) /cn11/rb15 a vss a vdd mclr pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 int0/rp7 (1) /cn23/rb7 flta1 (2) /ascl1/rp6 (1) /cn24/rb6 fltb1 (2) /asda1/rp5 (1) /cn27/rb5 v dd v ss an15/rp21 (1) /cn26/rc5 an12/rp20 (1) /cn25/rc4 an11/rp19 (1) /cn28/rc3 ra9 pgec3/sosco/an10/t1ck/cn0/ra4 dspic33fj32mc104 pwm1l2/rp13 (1) /cn13/rb13 pwm1h2/rp12 (1) /cn14/rb12 pwm1l3/rp11 (1) /cn15/rb11 pwm1h3/rp10 (1) /cn16/rb10 v cap v ss rp25 (1) /cn19/rc9 rp24 (1) /cn20/rc8 rp23 (1) /cn17/rc7 sda1/rp9 (1) /cn21/rb9 rp22 (1) /cn18/rc6 peged3/sosci/an9/rp4 (1) /cn1/rb4 ra8 osc2/clk0/cn29/ra3 osc1/clki/cn30/ra2 v ss v dd an8/rp18 (1) /cn10/rc2 an7/rp17 (1) /cn9/rc1 an6/rp16 (1) /cn8/rc0 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the pwm fault pins are enabled and asserted during any reset event. refer to section 15.2 ?pwm faults? for more information on the pwm faults.
? 2011-2014 microchip technology inc. ds70000652f-page 19 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 pin diagrams (continued) dspic33fj32gp104 44-pin qfn (2) 44 12 11 23 24 25 26 27 28 29 30 31 32 33 13 14 15 16 17 18 19 20 21 22 10 9 8 7 6 5 4 3 2 1 43 42 41 40 39 38 37 36 35 34 = pins are up to 5v tolerant ra10 ra7 rtcc/rp14 (1) /cn12/rb14 rp15 (1) /cn11/rb15 a vss a vdd mclr pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an6/rp16 (1) /cn8/rc0 an7/rp17 (1) /cn9/rc1 an8/rp18 (1) /cn10/rc2 v dd v ss osc1/clki/cn30/ra2 osc2/clko/cn29/ra3 ra8 pged3/sosci/an9/rp4 (1) /cn1/rb4 scl1/rp8 (1) /cn22/rb8 int0/rp7 (1) /cn23/rb7 ascl1/rp6 (1) /cn24/rb6 asda1/rp5 (1) /cn27/rb5 v dd v ss an15/rp21 (1) /cn26/rc5 an12/rp20 (1) /cn25/rc4 an11/rp19 (1) /cn28/rc3 ra9 pgec3/sosco/an10/t1ck/cn0/ra4 rp13 (1) /cn13/rb13 rp12 (1) /cn14/rb12 rp11 (1) /cn15/rb11 rp10 (1) /cn16/rb10 v cap v ss rp25 (1) /cn19/rc9 rp24 (1) /cn20/rc8 rp23 (1) /cn17/rc7 rp22 (1) /cn18/rc6 sda1/rp9 (1) /cn21/rb9 note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal pad at the bottom of the device is not c onnected to any pins and is recommended to be connected to v ss externally.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 20 ? 2011-2014 microchip technology inc. pin diagrams (continued) dspic33fj32mc104 44-pin qfn (2) 44 12 11 23 24 25 26 27 28 29 30 31 32 33 13 14 15 16 17 18 19 20 21 22 10 9 8 7 6 5 4 3 2 1 43 42 41 40 39 38 37 36 35 34 = pins are up to 5v tolerant ra10 ra7 pwm1h1/rtcc/rp14 (1) /cn12/rb14 pwm1l1/rp15 (1) /cn11/rb15 a vss a vdd mclr pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an6/rp16 (1) /cn8/rc0 an7/rp17 (1) /cn9/rc1 an8/rp18 (1) /cn10/rc2 v dd v ss osc1/clki/cn30/ra2 osc2/clko/cn29/ra3 ra8 pged3/sosci/an9/rp4 (1) /cn1/rb4 scl1/rp8 (1) /cn22/rb8 int0/rp7 (1) /cn23/rb7 flta1 (3) /ascl1/rp6 (1) /cn24/rb6 fltb1 (3) /asda1/rp5 (1) /cn27/rb5 v dd v ss an15/rp21 (1) /cn26/rc5 an12/rp20 (1) /cn25/rc4 an11/rp19 (1) /cn28/rc3 ra9 pgec3/sosco/an10/t1ck/cn0/ra4 pwm1l2/rp13 (1) /cn13/rb13 pwm1h2/rp12 (1) /cn14/rb12 pwm1l3/rp11 (1) /cn15/rb11 pwm1h3/rp10 (1) /cn16/rb10 v cap v ss rp25 (1) /cn19/rc9 rp24 (1) /cn20/rc8 rp23 (1) /cn17/rc7 rp22 (1) /cn18/rc6 sda1/rp9 (1) /cn21/rb9 note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal pad at the bottom of the device is not c onnected to any pins and is recommended to be connected to v ss externally. 3: the pwm fault pins are enabled and asserted during any reset event. refer to section 15.2 ?pwm faults? for more information on the pwm faults.
? 2011-2014 microchip technology inc. ds70000652f-page 21 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 pin diagrams (continued) dspic33fj32gp104 44-pin tla (2) = pins are up to 5v tolerant ra10 ra7 rtcc/rp14 (1) /cn12/rb14 rp15 (1) /cn11/rb15 a vss a vdd mclr pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 an4/c3inc/c2inc/rp2 (1) /cn6/rb2 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an6/rp16 (1) /cn8/rc0 an7/rp17 (1) /cn9/rc1 an8/rp18 (1) /cn10/rc2 v dd v ss osc1/clki/cn30/ra2 osc2/clko/cn29/ra3 ra8 pged3/sosci/an9/rp4 (1) /cn1/rb4 scl1/rp8 (1) /cn22/rb8 int0/rp7 (1) /cn23/rb7 ascl1/rp6 (1) /cn24/rb6 asda1/rp5 (1) /cn27/rb5 v dd v ss an15/rp21 (1) /cn26/rc5 an12/rp20 (1) /cn25/rc4 an11/rp19 (1) /cn28/rc3 ra9 pgec3/sosco/an10/t1ck/cn0/ra4 rp13 (1) /cn13/rb13 rp12 (1) /cn14/rb12 rp11 (1) /cn15/rb11 rp10 (1) /cn16/rb10 v cap v ss rp25 (1) /cn19/rc9 rp24 (1) /cn20/rc8 rp23 (1) /cn17/rc7 rp22 (1) /cn18/rc6 sda1/rp9 (1) /cn21/rb9 34 33 32 31 30 29 28 27 26 25 24 23 22 21 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 44 43 42 41 36 35 40 39 38 37 note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal pad at the bottom of the device is not c onnected to any pins and is recommended to be connected to v ss externally.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 22 ? 2011-2014 microchip technology inc. pin diagrams (continued) dspic33fj32mc104 44-pin tla (2) = pins are up to 5v tolerant ra10 ra7 pwm1h1/rtcc/rp14 (1) /cn12/rb14 pwm1l1/rp15 (1) /cn11/rb15 a vss a vdd mclr pged2/an0/c3inb/c1ina/cted1/cn2/ra0 pgec2/an1/c3ina/c1inb/cted2/cn3/ra1 pged1/an2/c2ina/c1inc/rp0 (1) /cn4/rb0 pgec1/an3/cv refin /cv refout /c2inb/c1ind/rp1 (1) /cn5/rb1 scl1/rp8 (1) /cn22/rb8 int0/rp7 (1) /cn23/rb7 flta1 (3) /ascl1/rp6 (1) /cn24/rb6 fltb1 (3) /asda1/rp5 (1) /cn27/rb5 v dd v ss an15/rp21 (1) /cn26/rc5 an12/rp20 (1) /cn25/rc4 an11/rp19 (1) /cn28/rc3 ra9 pgec3/sosco/an10/t1ck/cn0/ra4 pwm1l2/rp13 (1) /cn13/rb13 pwm1h2/rp12 (1) /cn14/rb12 pwm1l3/rp11 (1) /cn15/rb11 pwm1h3/rp10 (1) /cn16/rb10 v cap v ss rp25 (1) /cn19/rc9 rp24 (1) /cn20/rc8 rp23 (1) /cn17/rc7 rp22 (1) /cn18/rc6 sda1/rp9 (1) /cn21/rb9 34 33 32 31 30 29 28 27 26 25 24 23 22 21 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 44 43 42 41 36 35 40 39 38 37 note 1: the rpn pins can be used by any remappable peripheral. see table 1 for the list of available peripherals. 2: the metal pad at the bottom of the device is not c onnected to any pins and is recommended to be connected to v ss externally. 3: the pwm fault pins are enabled and asserted during any reset event. refer to section 15.2 ?pwm faults? for more information on the pwm faults. an4/c3inc/c2inc/rp2 (1) /cn6/rb2 an5/c3ind/c2ind/rp3 (1) /cn7/rb3 an6/rp16 (1) /cn8/rc0 an7/rp17 (1) /cn9/rc1 an8/rp18 (1) /cn10/rc2 v dd v ss osc1/clki/cn30/ra2 osc2/clko/cn29/ra3 ra8 pged3/sosci/an9/rp4 (1) /cn1/rb4
? 2011-2014 microchip technology inc. ds70000652f-page 23 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table of contents 1.0 device overview ............................................................................................................. ........................................................... 27 2.0 guidelines for getting started with 16-bit digital signal controllers ....................................................... ................................... 33 3.0 cpu......................................................................................................................... ................................................................... 37 4.0 memory organization ......................................................................................................... ........................................................ 49 5.0 flash program memory........................................................................................................ ...................................................... 83 6.0 resets ..................................................................................................................... .................................................................. 87 7.0 interrupt controller ........................................................................................................ ............................................................. 95 8.0 oscillator configuration ..................................... ............................................................... ........................................................ 125 9.0 power-saving features....................................................................................................... ..................................................... 133 10.0 i/o ports .................................................................................................................. ................................................................. 139 11.0 timer1 ..................................................................................................................... ................................................................. 165 12.0 timer2/3 and timer4/5 ...................................................................................................... ....................................................... 167 13.0 input capture.............................................................................................................. .............................................................. 175 14.0 output compare............................................................................................................. .......................................................... 177 15.0 motor control pwm module ................................................................................................... .................................................. 181 16.0 serial peripheral interface (spi).......................................................................................... ..................................................... 197 17.0 inter-integrated circuit? (i 2 c?)............................................................................................................................ .................. 203 18.0 universal asynchronous receiver transmitter (uart) ......................................................................... .................................. 211 19.0 10-bit analog-to-digital converter (adc)................................................................................... .............................................. 217 20.0 comparator module.......................................................................................................... ........................................................ 231 21.0 real-time clock and calendar (rtcc) ....................................................................................... ........................................... 243 22.0 charge time measurement unit (ctmu) ....................................................................................... ........................................ 255 23.0 special features ........................................................................................................... ........................................................... 261 24.0 instruction set summary .................................................................................................... ...................................................... 269 25.0 development support........................................................................................................ ....................................................... 277 26.0 electrical characteristics ................................................................................................. ......................................................... 281 27.0 high-temperature electrical characteristics................................................................................ ............................................ 339 28.0 packaging information...................................................................................................... ........................................................ 343 appendix a: revision history................................................................................................... .......................................................... 373 index .......................................................................................................................... ....................................................................... 381 the microchip web site ......................................................................................................... ............................................................ 387 customer change notification service ........................................................................................... ................................................... 387 customer support............................................................................................................... ............................................................... 387 product identification system .................................................................................................. .......................................................... 389
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 24 ? 2011-2014 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000000a is ve rsion a of document ds30000000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2011-2014 microchip technology inc. ds70000652f-page 25 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 referenced sources this device data sheet is based on the following individual chapters of the ?dspic33/pic24 family ref- erence manual? . these documents should be considered as the primary reference for the operation of a particular module or device feature. ? ?cpu? (ds70204) ? ?data memory? (ds70202) ? ?program memory? (ds70203) ? ?flash programming? (ds70191) ? ?reset? (ds70192) ? ?watchdog timer and power-saving modes? (ds70196) ? ?timers? (ds70205) ? ?input capture? (ds70198) ? ?output compare? (ds70209) ? ?motor control pwm? (ds70187) ? ?analog-to-digital converter (adc)? (ds70183) ? ?uart? (ds70188) ? ?serial peripheral interface (spi)? (ds70206) ? ?inter-integrated circuit? (i 2 c?)? (ds70195) ? ?codeguard security? (ds70199) ? ?programming and diagnostics? (ds70207) ? ?device configuration? (ds70194) ? ?i/o ports with peripheral pin select (pps)? (ds70190) ? ?real-time clock and calendar (rtcc)? (ds70301) ? ?introduction (part vi)? (ds70655) ? ?oscillator (part vi)? (ds70644) ? ?interrupts (part vi)? (ds70633) ? ?comparator with blanking? (ds70647) ? ?charge time measurement unit (ctmu)? (ds70635) note 1: to access the documents listed below, browse to the documentation section of the dspic33fj16mc102 product page of the microchip web site ( www.microchip.com ). in addition to parameters, features and other documentation, the resulting page provides links to the related family reference manual sections.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 26 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 27 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 1.0 device overview this data sheet contains device-specific information for dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/ mc)101/102/104 digital signal controller (dsc) devices. these devices cont ain extensive digital signal processor (dsp) functionality with a high-performance, 16-bit microcontroller (mcu) architecture. figure 1-1 shows a general block diagram of the core and peripheral modules in the dspic33fj16(gp/ mc)101/102 and dspic33fj32(gp/mc)101/102/104 family of devices. ta bl e 1 - 1 lists the functions of the various pins shown in the pinout diagrams. note: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices. however, it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the latest family reference sections of the ?dspic33/pic24 family reference manual? , which are available from the microchip web site ( www.microchip.com ).
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 28 ? 2011-2014 microchip technology inc. figure 1-1: dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 block diagram 16 osc1/clki osc2/clko v dd , v ss timing generation mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset precision reference band gap frc/lprc oscillators regulator voltage v cap ic1-ic3 i2c1 porta instruction decode and control 16 16-bit alu 23 23 24 23 instruction reg 16 ea mux 16 16 8 interrupt controller data latch address latch address latch program memory data latch literal data 16 16 16 16 data latch address latch x ram y ram y data bus x data bus dsp engine divide support control signals to various blocks adc1 timers portb address generator units 1-5 cnx uart1 oc/ pwm1-2 rtcc pwm 6-ch remappable pins spi1 ctmu external interrupts 1-3 comparators 1-3 note: not all pins or features are implemented on all device pinout configurations. see the ? pin diagrams ? section for the specific pins and features present on each device. psv and table data access control block 16 pch program counter pcu stack control logic loop control logic pcl 16 rom latch 16 16 x 16 w register array
? 2011-2014 microchip technology inc. ds70000652f-page 29 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 1-1: pinout i/o descriptions pin name pin type buffer type pps description an0-an12, an15 ( 5 ) i analog no analog input channels. clki clko i o st/cmos ? no no external clock source input. always associated with osc1 pin function. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. always associated with osc2 pin function. osc1 osc2 i i/o st/cmos ? no no oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. sosci sosco i o st/cmos ? no no 32.768 khz low-power oscillator crystal input; cmos otherwise. 32.768 khz low-power oscillator crystal output. cn0-cn30 ( 5 ) i st no change notification inputs. can be software programmable for internal weak pull-ups on all inputs. ic1-ic3 i st yes capture inputs 1/2/3. ocfa oc1-oc2 i o st ? yes yes compare fault a input (for compare channels 1 and 2). compare outputs 1/2. int0 int1 int2 i i i st st st no yes yes external interrupt 0. external interrupt 1. external interrupt 2. ra0-ra4, ra7-ra10 ( 5 ) i/o st no porta is a bidirectional i/o port. rb0-rb15 ( 5 ) i/o st no portb is a bidirectional i/o port. rc0-rc9 ( 5 ) i/o st no portc is a bidirectional i/o port. t1ck t2ck t3ck t4ck ( 6 ) t5ck ( 6 ) i i i i i st st st st st no yes yes yes yes timer1 external clock input. timer2 external clock input. timer3 external clock input. timer4 external clock input. timer5 external clock input. u1cts u1rts u1rx u1tx i o i o st ? st ? yes yes yes yes uart1 clear-to-send. uart1 ready-to-send. uart1 receive. uart1 transmit. sck1 sdi1 sdo1 i/o i o st st ? yes yes yes synchronous serial clock input/output for spi1. spi1 data in. spi1 data out. legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input pps = peripheral pin select note 1: an external pull-down resistor is required for the flta1 pin in dspic33fjxxmc101 (20-pin) devices. 2: the flta1 pin and the pwm1lx/pwm1hx pins are available in dspic(16/32)mc10x devices only. 3: the fltb1 pin is available in dspic(16/32)mc102/104 devices only. 4: the pwm fault pins are enabled during any reset event. refer to section 15.2 ?pwm faults? for more information on the pwm faults. 5: not all pins are available on all devices. refer to the specific device in the ?pin diagrams? section for availability. 6: these pins are available in dspic33fj32(gp/mc)104 (44-pin) devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 30 ? 2011-2014 microchip technology inc. scl1 sda1 ascl1 asda1 i/o i/o i/o i/o st st st st no no no no synchronous serial clock input/output for i2c1. synchronous serial data input/output for i2c1. alternate synchronous serial clock input/output for i2c1. alternate synchronous serial data input/output for i2c1. flta1 ( 1 , 2 , 4 ) fltb1 ( 3 , 4 ) pwm1l1 pwm1h1 pwm1l2 pwm1h2 pwm1l3 pwm1h3 i i o o o o o o st st ? ? ? ? ? ? no no no no no no no no pwm1 fault a input. pwm1 fault b input. pwm1 low output 1. pwm1 high output 1. pwm1 low output 2. pwm1 high output 2. pwm1 low output 3. pwm1 high output 3. rtcc o digital no rtcc alarm output. ctpls cted1 cted2 o i i digital digital digital yes no no ctmu pulse output. ctmu external edge input 1. ctmu external edge input 2. cv refin cv refout c1ina c1inb c1inc c1ind c1out c2ina c2inb c2inc c2ind c2out c3ina c3inb c3inc c3ind c3out i o i i i i o i i i i o i i i i o analog analog analog analog analog analog digital analog analog analog analog digital analog analog analog analog digital no no no no no no yes no no no no yes no no no no yes comparator voltage positive reference input. comparator voltage positive reference output. comparator 1 positive input a. comparator 1 negative input b. comparator 1 negative input c. comparator 1 negative input d. comparator 1 output. comparator 2 positive input a. comparator 2 negative input b. comparator 2 negative input c. comparator 2 negative input d. comparator 2 output. comparator 3 positive input a. comparator 3 negative input b. comparator 3 negative input c. comparator 3 negative input d. comparator 3 output. pged1 pgec1 pged2 pgec2 pged3 pgec3 i/o i i/o i i/o i st st st st st st no no no no no no data i/o pin for programming/debugging communication channel 1. clock input pin for programming/debugging communication channel 1. data i/o pin for programming/debugging communication channel 2. clock input pin for programming/debugging communication channel 2. data i/o pin for programming/debugging communication channel 3. clock input pin for programming/debugging communication channel 3. mclr i/p st no master clear (reset) input. this pin is an active-low reset to the device. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type pps description legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input pps = peripheral pin select note 1: an external pull-down resistor is required for the flta1 pin in dspic33fjxxmc101 (20-pin) devices. 2: the flta1 pin and the pwm1lx/pwm1hx pins are available in dspic(16/32)mc10x devices only. 3: the fltb1 pin is available in dspic(16/32)mc102/104 devices only. 4: the pwm fault pins are enabled during any reset event. refer to section 15.2 ?pwm faults? for more information on the pwm faults. 5: not all pins are available on all devices. refer to the specific device in the ?pin diagrams? section for availability. 6: these pins are available in dspic33fj32(gp/mc)104 (44-pin) devices only.
? 2011-2014 microchip technology inc. ds70000652f-page 31 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 av dd p p no positive supply for analog modules. this pin must be connected at all times. av dd is connected to v dd in the 18-pin dspic33fjxxgp101 and 20-pin dspic33fjxxmc101 devices. in all other devices, av dd is separated from v dd . av ss p p no ground reference for analog modules. av ss is connected to v ss in the 18-pin dspic33fjxxgp101 and 20-pin dspic33fjxxmc101 devices. in all other devices, av ss is separated from v ss . v dd p ? no positive supply for peripheral logic and i/o pins. v cap p ? no cpu logic filter capacitor connection. v ss p ? no ground reference for logic and i/o pins. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type pps description legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input pps = peripheral pin select note 1: an external pull-down resistor is required for the flta1 pin in dspic33fjxxmc101 (20-pin) devices. 2: the flta1 pin and the pwm1lx/pwm1hx pins are available in dspic(16/32)mc10x devices only. 3: the fltb1 pin is available in dspic(16/32)mc102/104 devices only. 4: the pwm fault pins are enabled during any reset event. refer to section 15.2 ?pwm faults? for more information on the pwm faults. 5: not all pins are available on all devices. refer to the specific device in the ?pin diagrams? section for availability. 6: these pins are available in dspic33fj32(gp/mc)104 (44-pin) devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 32 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 33 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 2.0 guidelines for getting started with 16-bit digital signal controllers 2.1 basic connection requirements getting started with the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family of 16-bit digital signal controllers (dscs) requires attention to a minimal set of device pin connections before proceeding with development. the following is a list of pin names, which must always be connected: ?all v dd and v ss pins (see section 2.2 ?decoupling capacitors? ) ?all av dd and av ss pins, if present on the device (regardless if adc module is not used) (see section 2.2 ?decoupling capacitors? ) ?v cap (see section 2.3 ?cpu logic filter capacitor connection (v cap )? ) ?mclr pin (see section 2.4 ?master clear (mclr) pin? ) ? pgecx/pgedx pins used for in-circuit serial programming? (icsp?) and debugging purposes (see section 2.5 ?icsp pins? ) ? osc1 and osc2 pins when external oscillator source is used (see section 2.6 ?external oscillator pins? ) 2.2 decoupling capacitors the use of decoupling capacitors on every pair of power supply pins, such as v dd , v ss , av dd and av ss , is required. consider the following criteria when using decoupling capacitors: ? value and type of capacitor: recommendation of 0.1 f (100 nf), 10v-20v. this capacitor should be a low-esr and have resonance frequency in the range of 20 mhz and higher. it is recommended that ceramic capacitors be used. ? placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended to place the capacitors on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. ? handling high-frequency noise: if the board is experiencing high-frequency noise, upward of tens of mhz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 f to 0.001 f. place this second capacitor next to the primary decoupling capacitor. in high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. for example, 0.1 f in parallel with 0.001 f. ? maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decoupling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing pcb track inductance. note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to com- plement the information in this data sheet, refer to the ?dspic33/pic24 family reference manual? . please see the microchip web site ( www.microchip.com ) for the latest ?dspic33/pic24 family reference manual? sections. 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 34 ? 2011-2014 microchip technology inc. figure 2-1: recommended minimum connection 2.2.1 tank capacitors on boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including dscs to supply a local power source. the value of the tank capacitor should be determined based on the trace resistance that con- nects the power supply source to the device and the maximum current drawn by the device in the applica- tion. in other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. typical values range from 4.7 f to 47 f. 2.3 cpu logic filter capacitor connection (v cap ) a low-esr (< 5 ohms) capacitor is required on the v cap pin, which is used to stabilize the voltage regulator output voltage. the v cap pin must not be connected to v dd , and must have a capacitor between 4.7 f and 10 f, 16v connected to ground. the type can be ceramic or tantalum. refer to section 26.0 ?electrical characteristics? for additional information. the placement of this capacitor should be close to the v cap . it is recommended that the trace length not exceed one-quarter inch (6 mm). refer to section 23.2 ?on-chip voltage regulator? for details. 2.4 master clear (mclr ) pin the mclr pin provides two specific device functions: ? device reset ? device programming and debugging during device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adversely affected. therefore, specific values of r and c will need to be adjusted based on the application and pcb requirements. for example, as shown in figure 2-2 , it is recommended that the capacitor c, be isolated from the mclr pin during programming and debugging operations. place the components shown in figure 2-2 within one-quarter inch (6 mm) from the mclr pin. figure 2-2: example of mclr pin connections dspic33f v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic c r v dd mclr 0.1 f ceramic v cap l1 (1) r1 10 f tantalum note 1: as an option, instead of a hard-wired connection, an inductor (l1) can be substituted between v dd and av dd to improve adc noise rejection. the inductor impedance should be less than 1 ? and the inductor capacity greater than 10 ma. where: f f cnv 2 ------------- - = f 1 2 ? lc ?? ----------------------- = l 1 2 ? fc ?? --------------------- - ?? ?? 2 = (i.e., adc conversion rate/2) note 1: r ? 10 k ? is recommended. a suggested starting value is 10 k ? . ensure that the mclr pin v ih and v il specifications are met. 2: r1 ? 470 ? will limit any current flowing into mclr from the external capacitor, c, in the event of mclr pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. c r1 (2) r (1) v dd mclr dspic33f jp
? 2011-2014 microchip technology inc. ds70000652f-page 35 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 2.5 icsp pins the pgecx and pgedx pins are used for in-circuit serial programming? (icsp?) and debugging pur- poses. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes, and capacitors on the pgecx and pgedx pins are not recommended as they will interfere with the programmer/debugger communi- cations to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alternately, refer to the ac/dc characteristics and timing requirements information in the ?dspic33f flash programming specification for devices with vol- atile configuration bits? (ds70659) for information on capacitive loading limits and pin voltage input high (v ih ) and voltage input low (v il ) requirements. ensure that the ?communication channel select? (i.e., pgecx/pgedx pins) programmed into the device matches the physical connections for the icsp to mplab ? icd 3 or mplab real ice?. for more information on icd 3 and real ice connection requirements, refer to the following documents that are available on the microchip web site. ? ?using mplab ? icd 3? (poster) (ds51765) ? ?mplab ? icd 3 design advisory? (ds51764) ? ?mplab ? real ice? in-circuit debugger user?s guide? ( ds51616) ? ?using mplab ? real ice?? (poster) (ds51749) 2.6 external oscillator pins many dscs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to section 8.0 ?oscillator configuration? for details). the oscillator circuit should be placed on the same side of the board as the device. also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or power traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. a suggested layout is shown in figure 2-3 . figure 2-3: suggested placement of the oscillator circuit 13 main oscillator guard ring guard trace secondary oscillator 14 15 16 17 18 19 20
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 36 ? 2011-2014 microchip technology inc. 2.7 oscillator value conditions on device start-up if the pll of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 mhz < f in < 8 mhz (for mspll mode) or 3 mhz < f in < 8 mhz (for ecpll mode) to comply with device pll start-up conditions. hspll mode is not supported. this means that if the external oscillator frequency is outside this range, the application must start-up in the frc mode first. the fixed pll settings of 4x after a por with an oscillator frequency outside this range will violate the device operating speed. once the device powers up, the application firmware can enable the pll and then perform a clock switch to the oscillator + pll clock source. note that clock switching must be enabled in the device configuration word. 2.8 configuration of analog and digital pins during icsp operations if mplab icd 3 or mplab real ice in-circuit emulator is selected as a debugger, it automatically initializes all of the analog-to-digital input pins (anx) as ?digital? pins, by setting all bits in the ad1pcfgl register. the bits in the register that correspond to the analog-to-digital pins that are initialized by mplab icd 3 or mplab real ice in-circuit emulator, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. if your application needs to use certain analog-to-digital pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ad1pcfgl register during initialization of the adc module. when mplab icd 3 or mplab real ice in-circuit emulator is used as a programmer, the user application firmware must correctly configure the ad1pcfgl register. automatic initialization of this register is only done during debugger operation. failure to correctly configure the register(s) will result in all analog-to-digital pins being recognized as analog input pins, resulting in the port value being read as a logic ? 0 ?, which may affect user application functionality. 2.9 unused i/os unused i/o pins should be configured as outputs and driven to a logic-low state. alternately, connect a 1k to 10k resistor between v ss and unused pins.
? 2011-2014 microchip technology inc. ds70000652f-page 37 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 3.0 cpu the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 cpu module has a 16-bit (data) modified harvard architecture with an enhanced instruction set, including significant support for dsp. the cpu has a 24-bit instruction word with a variable length opcode field. the program counter (pc) is 23 bits wide and addresses up to 4m x 24 bits of user program memory space. the actual amount of program memory implemented varies by device. a single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. all instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move ( mov.d ) instruction and the table instructions. overhead-free program loop constructs are supported using the do and repeat instructions, both of which are interruptible at any point. the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices have six- teen, 16-bit working registers in the programmer?s model. each of the working registers can serve as a data, address, or address offset register. the 16th working register (w15) operates as a software stack pointer (ssp) for interrupts and calls. there are two classes of instruction in the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/ mc)101/102/104 devices: mcu and dsp. these two instruction classes are seamlessly integrated into a sin- gle cpu. the instruction set includes many addressing modes and is designed for optimum c compiler effi- ciency. for most instructions, dspic33fj16(gp/ mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices are capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. as a result, three parameter instructions can be supported, allowing a + b = c operations to be executed in a single cycle. a block diagram of the cpu is shown in figure 3-1 , and the programmer?s model for the dspic33fj16(gp/ mc)101/102 and dspic33fj32(gp/mc)101/102/104 is shown in figure 3-2 . 3.1 data addressing overview the data space can be addressed as 32k words or 64 kbytes and is split into two blocks, referred to as x and y data memory. each memory block has its own independent address generation unit (agu). the mcu class of instructions operates solely through the x memory agu, which accesses the entire memory map as one linear data space. certain dsp instructions operate through the x and y agus to support dual operand reads, which splits the data address space into two parts. the x and y data space boundary is device-specific. overhead-free circular buffers (modulo addressing mode) are supported in both x and y address spaces. the modulo addressing removes the software boundary checking overhead for dsp algorithms. furthermore, the x agu circular addressing can be used with any of the mcu class of instructions. the x agu also supports bit-reversed addressing to greatly simplify input or output data reordering for radix-2 fft algorithms. the upper 32 kbytes of the data space memory map can optionally be mapped into program space at any 16k program word boundary defined by the 8-bit program space visibility page (psvpag) register. the program-to-data-space mapping feature lets any instruction access program space as if it were data space. 3.2 dsp engine overview the dsp engine features a high-speed, 17-bit by 17-bit multiplier, a 40-bit alu, two 40-bit saturating accumula- tors and a 40-bit bidirectional barrel shifter. the barrel shifter is capable of shifting a 40-bit value up to 16 bits right or left, in a single cycle. the dsp instructions oper- ate seamlessly with all other instructions and have been designed for optimal real-time performance. the mac instruction and other associated instructions can concur- rently fetch two data operands from memory, while multiplying two w registers and accumulating and option- ally saturating the result in the same cycle. this instruc- tion functionality requires that the ram data space be split for these instructions and linear for all others. data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space. note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to ?cpu? (ds70204) in the ?dspic33/pic24 family reference man- ual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 38 ? 2011-2014 microchip technology inc. 3.3 special mcu features the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 features a 17-bit by 17-bit, single-cycle multiplier that is shared by both the mcu alu and dsp engine. the multiplier can per- form signed, unsigned and mixed-sign multiplication. using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0). the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 supports 16/16 and 32/16 divide operations, both fractional and integer. all divide instructions are iterative operations. they must be executed within a repeat loop, resulting in a total execution time of 19 instruction cycles. the divide operation can be interrupted during any of those 19 cycles without loss of data. a 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a single cycle. the barrel shifter can be used by both mcu and dsp instructions. figure 3-1: dspic33fj16(gp/mc)101/ 102 and dspic33fj32(gp/mc)101/102/104 cpu core block diagram instruction decode and control pch program counter 16-bit alu 24 23 instruction reg pcu 16 x 16 w register array rom latch interrupt controller stack control logic loop control logic data latch address latch control signals to various blocks literal data 16 16 16 to peripheral modules data latch address latch 16 x ram y ram address generator units 16 y data bus x data bus dsp engine divide support 16 16 23 23 16 8 psv and table data access control block 16 16 16 16 program memory data latch address latch pcl ea mux
? 2011-2014 microchip technology inc. ds70000652f-page 39 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 3-2: dspic33fj16(gp/mc)101/ 102 and dspic33fj32(gp/mc)101/102/104 programmer?s model pc22 pc0 7 0 d0 d15 program counter data table page address status register working registers dsp operand registers w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12/dsp offset w13/dsp write back w14/frame pointer w15/stack pointer dsp address registers ad39 ad0 ad31 dsp accumulators acca accb 7 0 program space visibility page address z 0 oa ob sa sb rcount 15 0 repeat loop counter dcount 15 0 do loop counter dostart 22 0 do loop start address ipl2 ipl1 splim stack pointer limit register ad15 srl push.s shadow do shadow oab sab 15 0 core configuration register legend corcon da dc ra n tblpag psvpag ipl0 ov w0/wreg srh do loop end address doend 22 c
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 40 ? 2011-2014 microchip technology inc. 3.4 cpu control registers register 3-1: sr: cpu status register r-0 r-0 r/c-0 r/c-0 r-0 r/c-0 r-0 r/w-0 oa ob sa ( 1 ) sb ( 1 ) oab sab da dc bit 15 bit 8 r/w-0 ( 3 ) r/w-0 ( 3 ) r/w-0 ( 3 ) r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl2 ( 2 ) ipl1 ( 2 ) ipl0 ( 2 ) ra n ov z c bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 oa: accumulator a overflow status bit 1 = accumulator a has overflowed 0 = accumulator a has not overflowed bit 14 ob: accumulator b overflow status bit 1 = accumulator b has overflowed 0 = accumulator b has not overflowed bit 13 sa: accumulator a saturation ?sticky? status bit ( 1 ) 1 = accumulator a is saturated or has been saturated at some time 0 = accumulator a is not saturated bit 12 sb: accumulator b saturation ?sticky? status bit ( 1 ) 1 = accumulator b is saturated or has been saturated at some time 0 = accumulator b is not saturated bit 11 oab: oa || ob combined accumulator overflow status bit 1 = accumulators a or b have overflowed 0 = neither accumulators a or b have overflowed bit 10 sab: sa || sb combined accumulator ?sticky? status bit 1 = accumulators a or b are saturated or have been saturated at some time in the past 0 = neither accumulator a or b are saturated this bit may be read or cleared (not set). clearing this bit will clear sa and sb . bit 9 da: do loop active bit 1 = do loop is in progress 0 = do loop is not in progress bit 8 dc: mcu alu half carry/borrow bit 1 = a carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = no carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred note 1: this bit can be read or cleared (not set). 2: the ipl<2:0> bits are concatenated with the ipl<3> bit (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read-only when nstdis = 1 (intcon1<15>).
? 2011-2014 microchip technology inc. ds70000652f-page 41 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 bit 7-5 ipl<2:0>: cpu interrupt priority level status bits ( 2 , 3 ) 111 = cpu interrupt priority level is 7 (15), user interrupts are disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) bit 4 ra: repeat loop active bit 1 = repeat loop is in progress 0 = repeat loop is not in progress bit 3 n: mcu alu negative bit 1 = result was negative 0 = result was non-negative (zero or positive) bit 2 ov: mcu alu overflow bit this bit is used for signed arithmetic (2?s complement). it indicates an overflow of a magnitude that causes the sign bit to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 1 z: mcu alu zero bit 1 = an operation that affects the z bit has set it at some time in the past 0 = the most recent operation that affects the z bit has cleared it (i.e., a non-zero result) bit 0 c: mcu alu carry/borrow bit 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred register 3-1: sr: cpu status register (continued) note 1: this bit can be read or cleared (not set). 2: the ipl<2:0> bits are concatenated with the ipl<3> bit (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read-only when nstdis = 1 (intcon1<15>).
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 42 ? 2011-2014 microchip technology inc. register 3-2: corcon: core control register u-0 u-0 u-0 r/w-0 r/w-0 r-0 r-0 r-0 ? ? ?usedt ( 1 ) dl2 dl1 dl0 bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-0 r/c-0 r/w-0 r/w-0 r/w-0 sata satb satdw accsat ipl3 ( 2 ) psv rnd if bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit -n = value at por ?1? = bit is set 0? = bit is cleared ?x = bit is unknown u = unimplemented bit, read as ?0? bit 15-13 unimplemented: read as ? 0 ? bit 12 us: dsp multiply unsigned/signed control bit 1 = dsp engine multiplies are unsigned 0 = dsp engine multiplies are signed bit 11 edt: early do loop termination control bit ( 1 ) 1 = terminates executing do loop at the end of current loop iteration 0 = no effect bit 10-8 dl<2:0>: do loop nesting level status bits 111 = 7 do loops are active ? ? ? 001 = 1 do loop is active 000 = 0 do loops are active bit 7 sata: acca saturation enable bit 1 = accumulator a saturation is enabled 0 = accumulator a saturation is disabled bit 6 satb: accb saturation enable bit 1 = accumulator b saturation is enabled 0 = accumulator b saturation is disabled bit 5 satdw: data space write from dsp engine saturation enable bit 1 = data space write saturation is enabled 0 = data space write saturation is disabled bit 4 accsat: accumulator saturation mode select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 ipl3: cpu interrupt priority level status bit 3 ( 2 ) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less bit 2 psv: program space visibility in data space enable bit 1 = program space is visible in data space 0 = program space is not visible in data space bit 1 rnd: rounding mode select bit 1 = biased (conventional) rounding is enabled 0 = unbiased (convergent) rounding is enabled bit 0 if: integer or fractional multiplier mode select bit 1 = integer mode is enabled for dsp multiply operations 0 = fractional mode is enabled for dsp multiply operations note 1: this bit will always read as ? 0 ?. 2: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level.
? 2011-2014 microchip technology inc. ds70000652f-page 43 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 3.5 arithmetic logic unit (alu) the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 alu is 16 bits wide, and is capable of addition, subtraction, bit shifts and logic operations. unless otherwise mentioned, arithmetic operations are 2?s complement in nature. depending on the operation, the alu can affect the values of the carry (c), zero (z), negative (n), over- flow (ov) and digit carry (dc) status bits in the sr register. the c and dc status bits operate as borrow and digit borrow bits, respectively, for subtraction operations. the alu can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. data for the alu operation can come from the w register array or data memory, depending on the addressing mode of the instruction. likewise, output data from the alu can be written to the w register array or a data memory location. refer to the ?16-bit mcu and dsc programmer?s reference manual? (ds70157) for information on the sr bits affected by each instruction. the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 cpu incorporates hardware support for both multiplication and division. this includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division. 3.5.1 multiplier using the high-speed, 17-bit x 17-bit multiplier of the dsp engine, the alu supports unsigned, signed or mixed-sign operation in several mcu multiplication modes: ? 16-bit x 16-bit signed ? 16-bit x 16-bit unsigned ? 16-bit signed x 5-bit (literal) unsigned ? 16-bit unsigned x 16-bit unsigned ? 16-bit unsigned x 5-bit (literal) unsigned ? 16-bit unsigned x 16-bit signed ? 8-bit unsigned x 8-bit unsigned 3.5.2 divider the divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: ? 32-bit signed/16-bit signed divide ? 32-bit unsigned/16-bit unsigned divide ? 16-bit signed/16-bit signed divide ? 16-bit unsigned/16-bit unsigned divide the quotient for all divide instructions ends up in w0 and the remainder in w1. the 16-bit signed and unsigned div instructions can specify any w register for both the 16-bit divisor (wn) and any w register (aligned) pair (w(m + 1):wm) for the 32-bit dividend. the divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 3.6 dsp engine the dsp engine consists of a high-speed, 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round and saturation logic). the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 is a single-cycle instruction flow architecture; therefore, concurrent operation of the dsp engine with mcu instruction flow is not possible. however, some mcu alu and dsp engine resources can be used concurrently by the same instruction (e.g., ed , edac ). the dsp engine can also perform inherent accumulator- to-accumulator operations that require no additional data. these instructions are add , sub and neg . the dsp engine has options selected through bits in the cpu core control register (corcon), as listed below: ? fractional or integer dsp multiply (if) ? signed or unsigned dsp multiply (us) ? conventional or convergent rounding (rnd) ? automatic saturation on/off for acca (sata) ? automatic saturation on/off for accb (satb) ? automatic saturation on/off for writes to data memory (satdw) ? accumulator saturation mode selection (accsat) a block diagram of the dsp engine is shown in figure 3-3 . table 3-1: dsp instructions summary instruction algebraic operation acc write back clr a = 0 yes ed a = (x ? y) 2 no edac a = a + (x ? y) 2 no mac a = a + (x * y) yes mac a = a + x 2 no movsac no change in a yes mpy a = x * y no mpy a = x 2 no mpy.n a = ? x * y no msc a = a ? x * y yes
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 44 ? 2011-2014 microchip technology inc. figure 3-3: dsp engine block diagram zero backfill sign-extend barrel shifter 40-bit accumulator a 40-bit accumulator b round logic x data bus to/from w array adder saturate negate 32 32 33 16 16 16 16 40 40 40 40 s a t u r a t e y data bus 40 carry/borrow out carry/borrow in 16 40 multiplier/scaler 17-bit
? 2011-2014 microchip technology inc. ds70000652f-page 45 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 3.6.1 multiplier the 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (q31) or 32-bit integer results. unsigned operands are zero-extended into the 17th bit of the multiplier input value. signed operands are sign-extended into the 17th bit of the multiplier input value. the output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value that is sign-extended to 40 bits. integer data is inherently represented as a signed 2?s complement value, where the most signifi- cant bit (msb) is defined as a sign bit. the range of an n-bit 2?s complement integer is -2 n-1 to 2 n-1 ? 1. ? for a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7fff) including 0. ? for a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7fff ffff). when the multiplier is configured for fractional multiplication, the data is represented as a 2?s complement fraction, where the msb is defined as a sign bit and the radix point is implied to lie just after the sign bit (qx format). the range of an n-bit 2?s complement fraction with this implied radix point is -1.0 to (1 ? 2 1-n ). for a 16-bit fraction, the q15 data range is -1.0 (0x8000) to 0.999969482 (0x7fff) including 0 and has a precision of 3.01518x10 -5 . in fractional mode, the 16 x 16 multiply operation generates a 1.31 product that has a precision of 4.65661 x 10 -10 . the same multiplier is used to support the mcu multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations. the mul instruction can be directed to use byte or word-sized operands. byte operands will direct a 16-bit result and word operands will direct a 32-bit result to the specified register(s) in the w array. 3.6.2 data accumulators and adder/subtracter the data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. it can select one of two accumulators (a or b) as its pre-accumulation source and post-accumulation destination. for the add and lac instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. 3.6.2.1 adder/subtracter, overflow and saturation the adder/subtracter is a 40-bit adder with an optional zero input into one side and either true or complement data into the other input. ? in the case of addition, the carry/b orrow input is active-high and the other input is true data (not complemented). ? in the case of subtraction, the carry/borrow input is active-low and the other input is complemented. the adder/subtracter generates overflow status bits, sa/sb and oa/ob, which are latched and reflected in the status register: ? overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. ? overflow into guard bits 32 through 39: this is a recoverable overflow. this bit is set whenever all the guard bits are not identical to each other. the adder has an additional saturation block that controls accumulator data saturation, if selected. it uses the result of the adder, the overflow status bits described previously, and the sat (corcon<7:6>) and accsat (corcon<4>) mode control bits to determine when and to what value, to saturate. six status register bits support saturation and overflow: ? oa: acca overflowed into guard bits ? ob: accb overflowed into guard bits ? sa: acca saturated (bit 31 overflow and saturation) or acca overflowed into guard bits and saturated (bit 39 overflow and saturation) ? sb: accb saturated (bit 31 overflow and saturation) or accb overflowed into guard bits and saturated (bit 39 overflow and saturation) ? oab: logical or of oa and ob ? sab: logical or of sa and sb the oa and ob bits are modified each time data passes through the adder/subtracter. when set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). the oa and ob bits can also optionally generate an arithmetic warning trap when oa and ob are set and the corresponding overflow trap flag enable bits (ovate, ovbte) in the intcon1 register are set (refer to section 7.0 ?interrupt controller? ). this allows the user application to take immediate action; for example, to correct system gain.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 46 ? 2011-2014 microchip technology inc. the sa and sb bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. when set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). when saturation is not enabled, sa and sb default to bit 39 overflow, and therefore, indicate that a catastrophic overflow has occurred. if the covte bit in the intcon1 register is set, the sa and sb bits will generate an arithmetic warning trap when saturation is disabled. the overflow and saturation status bits can optionally be viewed in the status register (sr) as the logical or of oa and ob (in bit oab) and the logical or of sa and sb (in bit sab). programmers can check one bit in the status register to determine whether either accumulator has overflowed, or one bit to determine whether either accumulator has saturated. this is useful for complex number arithmetic, which typically uses both accumulators. the device supports three saturation and overflow modes: ? bit 39 overflow and saturation: when bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 value (0x7fffffffff) or maximally negative 9.31 value (0x8000000000) into the target accumulator. the sa or sb bit is set and remains set until cleared by the user application. this condi- tion is referred to as ?super saturation? and provides protection against erroneous data or unexpected algorithm problems (such as gain calculations). ? bit 31 overflow and saturation: when bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007fffffff) or maximally nega- tive 1.31 value (0x0080000000) into the target accumulator. the sa or sb bit is set and remains set until cleared by the user application. when this saturation mode is in effect, the guard bits are not used, so the oa, ob or oab bits are never set. ? bit 39 catastrophic overflow: the bit 39 overflow status bit from the adder is used to set the sa or sb bit, which remains set until cleared by the user application. no saturation operation is performed and the accumulator is allowed to overflow, destroying its sign. if the covte bit in the intcon1 register is set, a catastrophic overflow can initiate a trap exception. 3.6.3 accumulator ?write back? the mac class of instructions (with the exception of mpy , mpy.n , ed and edac ) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator which is not targeted by the instruc- tion into data space memory. the write is performed across the x bus into combined x and y address space. the following addressing modes are supported: ? w13, register direct: the rounded contents of the non-target accumulator are written into w13 as a 1.15 fraction. ? [w13]+ = 2, register indirect with post-increment: the rounded contents of the non-target accumu- lator are written into the address pointed to by w13 as a 1.15 fraction. w13 is then incremented by 2 (for a word write). 3.6.3.1 round logic the round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). the round mode is determined by the state of the rnd bit in the corcon register. it generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic. if rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word (lsw) is simply discarded. conventional rounding will zero-extend bit 15 of the accumulator and will add it to the accxh word (bits 16 through 31 of the accumulator). ? if the accxl word (bits 0 through 15 of the accu- mulator) is between 0x8000 and 0xffff (0x8000 included), accxh is incremented. ? if accxl is between 0x0000 and 0x7fff, accxh is left unchanged. a consequence of this algorithm is that over a succes- sion of random rounding operations, the value tends to be biased slightly positive. convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when accxl equals 0x8000. in this case, the least significant bit (lsb), bit 16 of the accumulator, of accxh is examined: ? if it is ? 1 ?, accxh is incremented. ? if it is ? 0 ?, accxh is not modified. assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate.
? 2011-2014 microchip technology inc. ds70000652f-page 47 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 the sac and sac.r instructions store either a truncated ( sac ), or rounded ( sac.r ) version of the contents of the target accumulator to data memory via the x bus, subject to data saturation (see section 3.6.3.2 ?data space write saturation? ). for the mac class of instructions, the accumulator write- back operation functions in the same manner, addressing combined mcu (x and y) data space though the x bus. for this class of instructions, the data is always subject to rounding. 3.6.3.2 data space write saturation in addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. the data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. these inputs are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. if the satdw bit in the corcon register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly: ? for input data greater than 0x007fff, data written to memory is forced to the maximum positive 1.15 value, 0x7fff. ? for input data less than 0xff8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. the msb of the source (bit 39) is used to determine the sign of the operand being tested. if the satdw bit in the corcon register is not set, the input data is always passed through unmodified under all conditions. 3.6.4 barrel shifter the barrel shifter can perform up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts, in a single cycle. the source can be either of the two dsp accumulators or the x bus (to support multi-bit shifts of register or memory data). the shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. a positive value shifts the operand right. a negative value shifts the operand left. a value of ? 0 ? does not modify the operand. the barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for dsp shift operations and a 16-bit result for mcu shift operations. data from the x bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 48 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 49 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 4.0 memory organization the device architecture features separate program and data memory spaces and buses. this architecture also allows the direct access of program memory from the data space during code execution. 4.1 program address space the program address memory space of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/ mc)101/102/104 devices is 4m instructions. the space is addressable by a 24-bit value derived either from the 23-bit program counter (pc) during program execution, or from table operation or data space remapping as described in section 4.6 ?interfacing program and data memory spaces? . user application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7fffff). the exception is the use of tblrd/tblwt operations, which use tblpag<7> to permit access to the configuration bits and device id sections of the configuration memory space. the memory maps for the dspic33fj16(gp/mc)101/ 102 and dspic33fj32(gp/mc)101/102/104 family of devices are shown in figure 4-1 and figure 4-2 . figure 4-1: program memo ry map for dspic33fj16(gp/mc)101/102 devices note: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. however, it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to ?data memory? (ds70202) and ?program memory? (ds70203) in the ?dspic33/pic24 family reference manual? , which are available from the microchip web site ( www.microchip.com ). reset address 0x000000 0x0000fe 0x000002 0x000100 device configuration user program flash memory 0x002bfc 0x002bfa (5.6k instructions) 0x800000 0xf80000 shadow registers 0xf80017 devid (2) 0xfefffe 0xff0000 0xfffffe 0xf7fffe unimplemented (read ? 0 ?s) goto instruction 0x000004 reserved 0x7ffffe reserved 0x000200 0x0001fe 0x000104 alternate vector table reserved interrupt vector table configuration memory space user memory space flash configuration words (1) 0x002coo 0x002bfe note 1: on reset, these bits are automatically copied into the device configur ation shadow registers. 0xf80018
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 50 ? 2011-2014 microchip technology inc. figure 4-2: program memo ry map for dspic33fj32(gp/mc)101/102/104 devices 0x000000 0x0000fe 0x000002 0x000100 device configuration user program flash memory 0x0057fc 0x0057fa (11.2k instructions) 0x800000 0xf80000 shadow registers 0xf80020 devid (2) 0xfefffe 0xff0000 0xfffffe 0xf7fffe unimplemented (read ? 0 ?s) 0x000004 reserved 0x7ffffe reserved 0x000200 0x0001fe 0x000104 alternate vector table reserved interrupt vector table configuration memory space user memory space flash configuration words (1) 0x005800 0x0057fe note 1: on reset, these bits are automatically copied into the device configuration shadow registers. 0xf80022 goto instruction reset address
? 2011-2014 microchip technology inc. ds70000652f-page 51 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 4.1.1 program memory organization the program memory space is organized in word- addressable blocks. although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. the lower word always has an even address, while the upper word has an odd address ( figure 4-3 ). program memory addresses are always word-aligned on the lower word and addresses are incremented or decremented by two during code execution. this arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. 4.1.2 interrupt and trap vectors all of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. a hardware reset vector is provided to redirect code execution from the default value of the pc on device reset to the actual start of code. a goto instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/ mc)101/102/104 devices also have two interrupt vec- tor tables (ivts), located from 0x000004 to 0x0000ff and 0x000100 to 0x0001ff. these vector tables allow each of the device interrupt sources to be handled by separate interrupt service routines (isrs). a more detailed discussion of the interrupt vector tables is provided in section 7.1 ?interrupt vector table? . figure 4-3: program memory organization 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 00000000 00000000 00000000 00000000 program memory ?phantom? byte (read as ? 0 ?) least significant word (lsw) most significant word (msw) instruction width 0x000001 0x000003 0x000005 0x000007 msw address (lsw address)
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 52 ? 2011-2014 microchip technology inc. 4.2 data address space the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family cpu has a separate 16-bit-wide data memory space. the data space is accessed using separate address generation units (agus) for read and write operations. the data memory maps is shown in figure 4-4 . all effective addresses (eas) in the data memory space are 16 bits wide and point to bytes within the data space. this arrangement gives a data space address range of 64 kbytes or 32k words. the lower half of the data memory space (that is, when ea<15> = 0 ) is used for implemented memory addresses, while the upper half (ea<15> = 1 ) is reserved for the program space visibility area (see section 4.6.3 ?reading data from program memory using program space visibility? ). microchip dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices implement up to 2 kbytes of data memory. should an ea point to a location outside of this area, an all-zero word or byte will be returned. 4.2.1 data space width the data memory space is organized in byte- addressable, 16-bit wide blo cks. data is aligned in data memory and registers as 16-bit words, but all data space eas resolve to bytes. the least significant bytes (lsbs) of each word have even addresses, while the most significant bytes (msbs) have odd addresses. 4.2.2 data memory organization and alignment to maintain backward compatibility with pic ? mcu devices and improve data space memory usage efficiency, the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family instruction set supports both word and byte operations. as a consequence of byte accessibility, all effective address calculations are internally scaled to step through word- aligned memory. for example, the core recognizes that post-modified register indirect addressing mode [ws++] will result in a value of ws + 1 for byte operations and ws + 2 for word operations. data byte reads will read the complete word that contains the byte, using the lsb of any ea to determine which byte to select. the selected byte is placed onto the lsb of the data path. that is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decoding but separate write lines. data byte writes only write to the corresponding side of the array or register that matches the byte address. all word accesses must be aligned to an even address. misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit mcu code. if a misaligned read or write is attempted, an address error trap is generated. if the error occurred on a read, the instruction in progress is completed. if the error occurred on a write, the instruction is executed but the write does not occur. in either case, a trap is then exe- cuted, allowing the system and/or user application to examine the machine state prior to execution of the address fault. all byte loads into any w register are loaded into the lsb. the msb is not modified. a sign-extend ( se ) instruction is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. alternately, for 16-bit unsigned data, user applications can clear the msb of any w register by executing a zero-extend ( ze ) instruction on the appropriate address. 4.2.3 sfr space the first 2 kbytes of the near data space, from 0x0000 to 0x07ff, is primarily occupied by special function registers (sfrs). these are used by the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/ mc)101/102/104 family core and peripheral modules for controlling the operation of the device. sfrs are distributed among the modules that they control and are generally grouped together by module. much of the sfr space contains unused addresses; these are read as ? 0 ?. 4.2.4 near data space the 8-kbyte area, between 0x0000 and 0x1fff, is referred to as the near data space. locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. additionally, the whole data space is addressable using the mov class of instructions, which support memory direct addressing mode with a 16-bit address field or by using indirect addressing mode with a working register as an address pointer. note: the actual set of peripheral features and interrupts varies by the device. refer to the corresponding device tables and pinout diagrams for device-specific information.
? 2011-2014 microchip technology inc. ds70000652f-page 53 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 4-4: data memory map for dspi c33fj16(gp/mc)101/102 devices with 1-kbyte ram 0x0000 0x07fe 0x0bfe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x07ff 0xffff optionally mapped into program memory 0x0801 0x0800 0x0c00 2-kbyte sfr space 1-kbyte sram space 0x8001 0x8000 x data unimplemented (x) y data ram (y) 0x09fe 0x0a00 0x09ff 0x0a01 0x0bff 0x0c01 0x1fff 0x1ffe 0x2001 0x2000 8-kbyte near data space x data ram (x) sfr space
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 54 ? 2011-2014 microchip technology inc. figure 4-5: data memory map for dspic3 3fj32(gp/mc)101/102/104 devices with 2-kbyte ram 0x0000 0x07fe 0x0ffe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x07ff 0xffff optionally mapped into program memory 0x0801 0x0800 0x1000 2 kbyte sfr space 2 kbyte sram space 0x8001 0x8000 sfr space x data unimplemented (x) y data ram (y) 0x0bfe 0x0c00 0x0bff 0x0c01 0x0fff 0x1001 0x1fff 0x1ffe 0x2001 0x2000 8 kbyte near data space x data ram (x)
? 2011-2014 microchip technology inc. ds70000652f-page 55 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 4.2.5 x and y data spaces the core has two data spaces, x and y. these data spaces can be considered either separate (for some dsp instructions), or as one unified linear address range (for mcu instructions). the data spaces are accessed using two address generation units (agus) and separate data paths. this feature allows certain instructions to concurrently fetch two words from ram, thereby enabling efficient execution of dsp algorithms such as finite impulse response (fir) filtering and fast fourier transform (fft). the x data space is used by all instructions and supports all addressing modes. x data space has separate read and write data buses. the x read data bus is the read data path for all instructions that view data space as combined x and y address space. it is also the x data prefetch path for the dual operand dsp instructions ( mac class). the y data space is used in concert with the x data space by the mac class of instructions ( clr , ed , edac , mac , movsac , mpy , mpy.n and msc ) to provide two concurrent data read paths. both the x and y data spaces support modulo addressing mode for all instructions, subject to addressing mode restrictions. bit-reversed addressing mode is only supported for writes to x data space. all data memory writes, including in dsp instructions, view data space as combined x and y address space. the boundary between the x and y data spaces is device-dependent and is not user-programmable. all effective addresses are 16 bits wide and point to bytes within the data space. therefore, the data space address range is 64 kbytes, or 32k words, although the implemented memory locations vary by device.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 56 ? 2011-2014 microchip technology inc. table 4-1: cpu core register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets wreg0 0000 working register 0 xxxx wreg1 0002 working register 1 xxxx wreg2 0004 working register 2 xxxx wreg3 0006 working register 3 xxxx wreg4 0008 working register 4 xxxx wreg5 000a working register 5 xxxx wreg6 000c working register 6 xxxx wreg7 000e working register 7 xxxx wreg8 0010 working register 8 xxxx wreg9 0012 working register 9 xxxx wreg10 0014 working register 10 xxxx wreg11 0016 working register 11 xxxx wreg12 0018 working register 12 xxxx wreg13 001a working register 13 xxxx wreg14 001c working register 14 xxxx wreg15 001e working register 15 0800 splim 0020 stack pointer limit register xxxx accal 0022 accumulator a low word register xxxx accah 0024 accumulator a high word register xxxx accau 0026 accumulator a upper word register xxxx accbl 0028 accumulator b low word register xxxx accbh 002a accumulator b high word register xxxx accbu 002c accumulator b upper word register xxxx pcl 002e program counter low word register 0000 pch 0030 ? ? ? ? ? ? ? ? program counter high byte register 0000 tblpag 0032 ? ? ? ? ? ? ? ? table page address pointer register 0000 psvpag 0034 ? ? ? ? ? ? ? ? program memory visibility page address pointer register 0000 rcount 0036 repeat loop counter register xxxx dcount 0038 dcount<15:0> xxxx dostartl 003a dostartl<15:1> 0xxxx dostarth 003c ? ? ? ? ? ? ? ? ? ?dostarth<5:0> 00xx doendl 003e doendl<15:1> 0xxxx doendh 0040 ? ? ? ? ? ? ? ? ? ? doendh 00xx sr 0042 oa ob sa sb oab sab da dc ipl2 ipl1 ipl0 ra n ov z c 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2011-2014 microchip technology inc. ds70000652f-page 57 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 corcon 0044 ? ? ? us edt dl2 dl1 dl0 sata satb satdw accsat ipl3 psv rnd if 0020 modcon 0046 xmoden ymoden ? ? bwm3 bwm2 bwm1 bwm0 ywm3 ywm2 ywm1 ywm0 xwm3 xwm2 xwm1 xwm0 0000 xmodsrt 0048 xs<15:1> 0 xxxx xmodend 004a xe<15:1> 1 xxxx ymodsrt 004c ys<15:1> 0 xxxx ymodend 004e ye<15:1> 1 xxxx xbrev 0050 bren xb<14:0> xxxx disicnt 0052 ? ? disable interrupts counter register 0000 table 4-1: cpu core register map (continued) sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 58 ? 2011-2014 microchip technology inc. table 4-2: change notificatio n register map for dspic33fjxxgp101 devices sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnen1 0060 ? ? ? cn12ie cn11ie ? ? ? ? ? cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0062 ? cn30ie cn29ie ? ? ? ? ? cn23ie cn22ie cn21ie ? ? ? ? ? 0000 cnpu1 0068 ? ? ? cn12pue cn11pue ? ? ? ? ? cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 006a ? cn30pue cn29pue ? ? ? ? ? cn23pue cn22pue cn21pue ? ? ? ? ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-3: change notificatio n register map for dspic33fjxxmc101 devices sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnen1 0060 ? cn14ie cn13ie cn12ie cn11ie ? ? ? ? ? cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0062 ? cn30ie cn29ie ? ? ? ? ? cn23ie cn22ie cn21ie ? ? ? ? ? 0000 cnpu1 0068 ? cn14pue cn13pue cn12pue cn11pue ? ? ? ? ? cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 006a ? cn30pue cn29pue ? ? ? ? ? cn23pue cn22pue cn21pue ? ? ? ? ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-4: change notification register map for dspic3 3fjxx(gp/mc)102 devices sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnen1 0060 cn15ie cn14ie cn13ie cn12ie cn11ie ? ? ? cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0062 ? cn30ie cn29ie ? cn27ie ? ? cn24ie cn23ie cn22ie cn21ie ? ? ? ? cn16ie 0000 cnpu1 0068 cn15pue cn14pue cn13pue cn12pue cn11pue ? ? ? cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 006a ? cn30pue cn29pue ? cn27pue ? ? cn24pue cn23pue cn22pue cn21pue ? ? ? ? cn16pue 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-5: change notification register map for dspic3 3fj32(gp/mc)104 devices sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnen1 0060 cn15ie cn13ie cn13ie cn12ie cn11ie cn10ie cn9ie cn8ie cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0062 ? cn30ie cn29ie cn28ie cn27ie cn26ie cn25ie cn24ie cn23ie cn22ie cn21ie cn20ie cn19ie cn18ie cn17ie cn16ie 0000 cnpu1 0068 cn15pue cn13pue cn13pue cn12pue cn11pue cn10pue cn9pue cn8pue cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 006a ? cn30pue cn29pue cn28pue cn27pue cn26pue cn25pue cn24pue cn23pue cn22pue cn21pue cn20pue cn19pue cn18pue cn17pue cn16pue 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2011-2014 microchip technology inc. ds70000652f-page 59 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 4-6: interrupt controller register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets intcon1 0080 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte sftacerr div0err ? matherr addrerr stkerr oscfail ? 0000 intcon2 0082 altivt disi ? ? ? ? ? ? ? ? ? ? ? int2ep int1ep int0ep 0000 ifs0 0084 ? ? ad1if u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if ? t1if oc1if ic1if int0if 0000 ifs1 0086 ? ?int2ift5if ( 2 ) t4if ( 2 ) ? ? ? ? ? ? int1if cnif cmif mi2c1if si2c1if 0000 ifs2 0088 ? ? ? ? ? ? ? ? ? ?ic3if ? ? ? ? ? 0000 ifs3 008a flta1if ( 1 ) rtcif ? ? ? ?pwm1if ( 1 ) ? ? ? ? ? ? ? ? ? 0000 ifs4 008c ? ?ctmuif ? ? ? ? ? ? ? ? ? ? ? u1eif fltb1if ( 3 ) 0000 iec0 0094 ? ? ad1ie u1txie u1rxie spi1ie spi1eie t3ie t2ie oc2ie ic2ie ? t1ie oc1ie ic1ie int0ie 0000 iec1 0096 ? ? int2ie t5ie ( 2 ) t4ie ( 2 ) ? ? ? ? ? ? int1ie cnie cmie mi2c1ie si2c1ie 0000 iec2 0098 ? ? ? ? ? ? ? ? ? ?ic3ie ? ? ? ? ? 0000 iec3 009a flta1ie ( 1 ) rtcie ? ? ? ?pwm1ie ( 1 ) ? ? ? ? ? ? ? ? ? 0000 iec4 009c ? ?ctmuie ? ? ? ? ? ? ? ? ? ? ? u1eie fltb1ie ( 3 ) 0000 ipc0 00a4 ? t1ip2 t1ip1 t1ip0 ? oc1ip2 oc1ip1 oc1ip0 ? ic1ip2 ic1ip1 ic1ip0 ?int0ip2:0> 4444 ipc1 00a6 ? t2ip2 t2ip1 t2ip0 ? oc2ip2 oc2ip1 oc2ip0 ? ic2ip2 ic2ip1 ic2ip0 ? ? ? ? 4440 ipc2 00a8 ? u1rxip2 u1rxip1 u1rxip0 ? spi1ip2 spi1ip1 spi1ip0 ? spi1eip2 spi1eip1 spi1eip0 ? t3ip2 t3ip1 t3ip0 4444 ipc3 00aa ? ? ? ? ? ? ? ? ? ad1ip2 ad1ip1 ad1ip0 ? u1txip2 u1txip1 u1txip0 0044 ipc4 00ac ? cnip2 cnip1 cnip0 ? cmip2 cmip1 cmip0 ? mi2c1ip2 mi2c1ip1 mi2c1ip0 ? si2c1ip2 si2c1ip1 si2c1ip0 4444 ipc5 00ae ? ? ? ? ? ? ? ? ? ? ? ? ? int1ip2 int1ip1 int1ip0 0004 ipc6 00b0 ?t4ip2 ( 2 ) t4ip1 ( 2 ) t4ip0 ( 2 ) ? ? ? ? ? ? ? ? ? ? ? ? 4000 ipc7 00b2 ? ? ? ? ? ? ? ? ? int2ip2 int2ip1 int2ip0 ?t5ip2 ( 2 ) t5ip1 ( 2 ) t5ip0 ( 2 ) 0044 ipc9 00b6 ? ? ? ? ? ? ? ? ? ic3ip2 ic3ip1 ic3ip0 ? ? ? ? 0040 ipc14 00c0 ? ? ? ? ? ? ? ? ?pwm1ip2 ( 1 ) pwm1ip1 ( 1 ) pwm1ip0 ( 1 ) ? ? ? ? 0040 ipc15 00c2 ?flta1ip2 ( 1 ) flta1ip1 ( 1 ) flta1ip0 ( 1 ) ? rtcip2 rtcip1 rtcip0 ? ? ? ? ? ? ? ? 4400 ipc16 00c4 ? ? ? ? ? ? ? ? ? u1eip2 u1eip1 u1eip0 ?fltb1ip2 ( 3 ) fltb1ip1 ( 3 ) fltb1ip0 ( 3 ) 0040 ipc19 00ca ? ? ? ? ? ? ? ? ? ctmuip2 ctmuip1 ctmuip0 ? ? ? ? 0040 inttreg 00e0 ? ? ? ? ilr3 ilr2 ilr1 ilr0 ? vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: these bits are available in dspic33fjxxmc10x devices only. 2: these bits are available in ds pic33fj32(gp/mc)10x devices only. 3: these bits are available in dspic33fj(16/32)mc102/104 devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 60 ? 2011-2014 microchip technology inc. table 4-7: timers register map fo r dspic33fj16(gp/mc)10x devices sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets tmr1 0100 timer1 register 0000 pr1 0102 period register 1 ffff t1con 0104 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? tsync tcs ? 0000 tmr2 0106 timer2 register 0000 tmr3hld 0108 timer3 holding register (for 32-bit timer operations only) xxxx tmr3 010a timer3 register 0000 pr2 010c period register 2 ffff pr3 010e period register 3 ffff t2con 0110 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t32 ?tcs ? 0000 t3con 0112 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-8: timers register map fo r dspic33fj32(gp/mc)10x devices sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets tmr1 0100 timer1 register 0000 pr1 0102 period register 1 ffff t1con 0104 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? tsync tcs ? 0000 tmr2 0106 timer2 register 0000 tmr3hld 0108 timer3 holding register (for 32-bit timer operations only) xxxx tmr3 010a timer3 register 0000 pr2 010c period register 2 ffff pr3 010e period register 3 ffff t2con 0110 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t32 ?tcs ? 0000 t3con 0112 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 tmr4 0114 timer4 register 0000 tmr5hld 0116 timer5 holding register (for 32-bit operations only) xxxx tmr5 0118 timer5 register 0000 pr4 011a period register 4 ffff pr5 011c period register 5 ffff t4con 011e ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t32 ?tcs ? 0000 t5con 0120 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2011-2014 microchip technology inc. ds70000652f-page 61 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 4-9: input capture register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ic1buf 0140 input capture 1 register xxxx ic1con 0142 ? ?icsidl ? ? ? ? ? ictmr ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic2buf 0144 input capture 2 register xxxx ic2con 0146 ? ?icsidl ? ? ? ? ? ictmr ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic3buf 0148 input capture 3 register xxxx ic3con 014a ? ?icsidl ? ? ? ? ? ictmr ici1 ici0 icov icbne icm2 icm1 icm0 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-10: output compare register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets oc1rs 0180 output compare 1 secondary register xxxx oc1r 0182 output compare 1 register xxxx oc1con 0184 ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm2 ocm1 ocm0 0000 oc2rs 0186 output compare 2 secondary register xxxx oc2r 0188 output compare 2 register xxxx oc2con 018a ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm2 ocm1 ocm0 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-11: 6-output pwm1 register map for dspic33fjxxmc10x devices sfr name sfr addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state p1tcon 01c0 pten ?ptsidl ? ? ? ? ? ptops3 ptops2 ptops1 ptops0 ptckps1 ptckps0 ptmod1 ptmod0 0000 0000 0000 0000 p1tmr 01c2 ptdir pwm1 timer count value register 0000 0000 0000 0000 p1tper 01c4 ? pwm1 time base period register 0111 1111 1111 1111 p1secmp 01c6 sevtdir pwm1 special event compare register 0000 0000 0000 0000 pwm1con1 01c8 ? ? ? ? ? pmod3 pmod2 pmod1 ? pen3h pen2h pen1h ? pen3l pen2l pen1l 0000 0000 0000 0000 pwm1con2 01ca ? ? ? ? sevops3 sevops2 sevops1 sevops0 ? ? ? ? ? iue osync udis 0000 0000 0000 0000 p1dtcon1 01cc dtbps1 dtbps0 dtb5 dtb4 dtb3 dtb2 dtb1 dtb0 dtaps1 dtaps0 dta5 dta4 dta3 dta2 dta1 dta0 0000 0000 0000 0000 p1dtcon2 01ce ? ? ? ? ? ? ? ? ? ? dts3a dts3i dts2a dts2i dts1a dts1i 0000 0000 0000 0000 p1fltacon 01d0 ? ? faov3h faov3l faov2h faov2l faov1h faov1l fltam ? ? ? ? faen3 faen2 faen1 0000 0000 0000 0111 p1fltbcon 01d2 ? ? fbov3h fbov3l fbov2h fbov2l fbov1h fbov1l fltbm ? ? ? ? fben3 fben2 fben1 0000 0000 0000 0111 p1ovdcon 01d4 ? ? povd3h povd3l povd2h povd2l povd1h povd1l ? ? pout3h pout3l pout2h pout2l pout1h pout1l 0011 1111 0000 0000 p1dc1 01d6 pwm1 duty cycle 1 register 0000 0000 0000 0000 p1dc2 01d8 pwm1 duty cycle 2 register 0000 0000 0000 0000 p1dc3 01da pwm1 duty cycle 3 register 0000 0000 0000 0000 pwm1key 01de pwmkey<15:0> 0000 0000 0000 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 62 ? 2011-2014 microchip technology inc. table 4-12: i2c1 register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets i2c1rcv 0200 ? ? ? ? ? ? ? ? i2c1 receive register 0000 i2c1trn 0202 ? ? ? ? ? ? ? ? i2c1 transmit register 00ff i2c1brg 0204 ? ? ? ? ? ? ? baud rate generator register 0000 i2c1con 0206 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c1stat 0208 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 i2c1add 020a ? ? ? ? ? ? i2c1 address register 0000 i2c1msk 020c ? ? ? ? ? ? i2c1 address mask register 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-13: uart1 register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets u1mode 0220 uarten ? usidl iren rtsmd ? uen1 uen0 wake lpback abaud urxinv brgh pdsel1 pdsel0 stsel 0000 u1sta 0222 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0110 u1txreg 0224 ? ? ? ? ? ? ? uart1 transmit register xxxx u1rxreg 0226 ? ? ? ? ? ? ? uart1 receive register 0000 u1brg 0228 baud rate generator prescaler 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-14: spi1 register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets spi1stat 0240 spien ? spisidl ? ? ? ? ? ?spirov ? ? ? ? spitbf spirbf 0000 spi1con1 0242 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 spi1con2 0244 frmen spifsd frmpol ? ? ? ? ? ? ? ? ? ? ? frmdly ? 0000 spi1buf 0248 spi1 transmit and receive buffer register 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2011-2014 microchip technology inc. ds70000652f-page 63 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 4-15: adc1 register map for dspic33fjxx(gp/mc)101 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adc1buf0 0300 adc1 data buffer 0 xxxx adc1buf1 0302 adc1 data buffer 1 xxxx adc1buf2 0304 adc1 data buffer 2 xxxx adc1buf3 0306 adc1 data buffer 3 xxxx adc1buf4 0308 adc1 data buffer 4 xxxx adc1buf5 030a adc1 data buffer 5 xxxx adc1buf6 030c adc1 data buffer 6 xxxx adc1buf7 030e adc1 data buffer 7 xxxx adc1buf8 0310 adc1 data buffer 8 xxxx adc1buf9 0312 adc1 data buffer 9 xxxx adc1bufa 0314 adc1 data buffer 10 xxxx adc1bufb 0316 adc1 data buffer 11 xxxx adc1bufc 0318 adc1 data buffer 12 xxxx adc1bufd 031a adc1 data buffer 13 xxxx adc1bufe 031c adc1 data buffer 14 xxxx adc1buff 031e adc1 data buffer 15 xxxx ad1con1 0320 adon ?adsidl ? ? ? form1 form0 ssrc2 ssrc1 ssrc0 ? simsam asam samp done 0000 ad1con2 0322 vcfg2 vcfg1 vcfg0 ? ? cscna chps1 chps0 bufs ? smpi3 smpi2 smpi1 smpi0 bufm alts 0000 ad1con3 0324 adrc ? ? samc4 samc3 samc2 samc1 samc0 adcs7 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 0000 ad1chs123 0326 ? ? ? ? ? ch123nb1 ch123nb0 ch123sb ? ? ? ? ? ch123na1 ch123na0 ch123sa 0000 ad1chs0 0328 ch0nb ? ? ch0sb4 ch0sb3 ch0sb2 ch0sb1 ch0sb0 ch0na ? ? ch0sa4 ch0sa3 ch0sa2 ch0sa1 ch0sa0 0000 ad1pcfgl 032c ? ? ? ? ? pcfg<10:9> ( 1 ) ? ? ? ? ?pcfg<3:0> 0000 ad1cssl 0330 ? ? ? ? ? css<10:9> ( 1 ) ? ? ? ? ? css<3:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: the pcfg<10:9> and css<10:9> bits are available in dspic33fj32(gp/mc)101/102 devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 64 ? 2011-2014 microchip technology inc. table 4-16: adc1 register map for dspic33fjxx(gp/mc)102 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adc1buf0 0300 adc1 data buffer 0 xxxx adc1buf1 0302 adc1 data buffer 1 xxxx adc1buf2 0304 adc1 data buffer 2 xxxx adc1buf3 0306 adc1 data buffer 3 xxxx adc1buf4 0308 adc1 data buffer 4 xxxx adc1buf5 030a adc1 data buffer 5 xxxx adc1buf6 030c adc1 data buffer 6 xxxx adc1buf7 030e adc1 data buffer 7 xxxx adc1buf8 0310 adc1 data buffer 8 xxxx adc1buf9 0312 adc1 data buffer 9 xxxx adc1bufa 0314 adc1 data buffer 10 xxxx adc1bufb 0316 adc1 data buffer 11 xxxx adc1bufc 0318 adc1 data buffer 12 xxxx adc1bufd 031a adc1 data buffer 13 xxxx adc1bufe 031c adc1 data buffer 14 xxxx adc1buff 031e adc1 data buffer 15 xxxx ad1con1 0320 adon ?adsidl ? ? ? form1 form0 ssrc2 ssrc1 ssrc0 ? simsam asam samp done 0000 ad1con2 0322 vcfg2 vcfg1 vcfg0 ? ? cscna chps1 chps0 bufs ? smpi3 smpi2 smpi1 smpi0 bufm alts 0000 ad1con3 0324 adrc ? ? samc4 samc3 samc2 samc1 samc0 adcs7 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 0000 ad1chs123 0326 ? ? ? ? ? ch123nb1 ch123nb0 ch123sb ? ? ? ? ? ch123na1 ch123na0 ch123sa 0000 ad1chs0 0328 ch0nb ? ? ch0sb4 ch0sb3 ch0sb2 ch0sb1 ch0sb0 ch0na ? ? ch0sa4 ch0sa3 ch0sa2 ch0sa1 ch0sa0 0000 ad1pcfgl 032c ? ? ? ? ? pcfg<10:9> ( 1 ) ? ? ?pcfg<5:0> 0000 ad1cssl 0330 ? ? ? ? ? css<10:9> ( 1 ) ? ? ?css<5:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: the pcfg<10:9> and css<10:9> bits are available in dspic33fj32(gp/mc)101/102 devices only.
? 2011-2014 microchip technology inc. ds70000652f-page 65 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 4-17: adc1 register map for dspic33fj32(gp/mc)104 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adc1buf0 0300 adc1 data buffer 0 xxxx adc1buf1 0302 adc1 data buffer 1 xxxx adc1buf2 0304 adc1 data buffer 2 xxxx adc1buf3 0306 adc1 data buffer 3 xxxx adc1buf4 0308 adc1 data buffer 4 xxxx adc1buf5 030a adc1 data buffer 5 xxxx adc1buf6 030c adc1 data buffer 6 xxxx adc1buf7 030e adc1 data buffer 7 xxxx adc1buf8 0310 adc1 data buffer 8 xxxx adc1buf9 0312 adc1 data buffer 9 xxxx adc1bufa 0314 adc1 data buffer 10 xxxx adc1bufb 0316 adc1 data buffer 11 xxxx adc1bufc 0318 adc1 data buffer 12 xxxx adc1bufd 031a adc1 data buffer 13 xxxx adc1bufe 031c adc1 data buffer 14 xxxx adc1buff 031e adc1 data buffer 15 xxxx ad1con1 0320 adon ?adsidl ? ? ? form1 form0 ssrc2 ssrc1 ssrc0 ? simsam asam samp done 0000 ad1con2 0322 vcfg2 vcfg1 vcfg0 ? ? cscna chps1 chps0 bufs ? smpi3 smpi2 smpi1 smpi0 bufm alts 0000 ad1con3 0324 adrc ? ? samc4 samc3 samc2 samc1 samc0 adcs7 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 0000 ad1chs123 0326 ? ? ? ? ? ch123nb1 ch123nb0 ch123sb ? ? ? ? ? ch123na1 ch123na0 ch123sa 0000 ad1chs0 0328 ch0nb ? ? ch0sb4 ch0sb3 ch0sb2 ch0sb1 ch0sb0 ch0na ? ? ch0sa4 ch0sa3 ch0sa2 ch0sa1 ch0sa0 0000 ad1pcfgl 032c pcfg15 ? ? pcfg<12:0> ( 1 ) 0000 ad1cssl 0330 css15 ? ? css12:0> ( 1 ) 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: the pcfg<10:9> and css<10:9> bits are available in dspic33fj32(gp/mc)104 devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 66 ? 2011-2014 microchip technology inc. table 4-18: ctmu register map file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ctmucon1 033a ctmuen ? ctmusidl tgen edgen edgseqen idissen cttrig ? ? ? ? ? ? ? ? 0000 ctmucon2 033c edg1mod edg1pol edg1sel3 edg1sel2 edg1sel1 edg1sel0 edg 2stat edg1stat edg2mod edg2pol edg 2sel3 edg2sel2 edg2sel1 edg2sel0 ? ? 0000 ctmuicon 033e itrim5 itrim4 itrim3 itrim2 itrim1 itrim0 irng1 irng0 ? ? ? ? ? ? ? ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-19: real-time clock and calendar register map file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets alrmval 0620 alarm value register window based on alrmptr<1:0> xxxx alcfgrpt 0622 alrmen chime amask3 amask2 amask1 amask0 alrmptr1 alrmptr0 arpt7 arpt6 arpt5 arpt4 arpt3 arpt2 arpt1 arpt0 0000 rtcval 0624 rtcc value register window based on rtcptr<1:0> xxxx rcfgcal 0626 rtcen ? rtcwren rtcsync halfsec rtcoe rtcptr1 rtcptr0 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-20: pad configuration register map file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets padcfg1 02fc ? ? ? ? ? ? ? ? ? ? ? ? ? ? rtsecsel ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2011-2014 microchip technology inc. ds70000652f-page 67 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 4-21: comparator register map file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cmstat 0650 cmsidl ? ? ? ? c3evt c2evt c1evt ? ? ? ? ? c3out c2out c1out 0000 cvrcon 0652 ? ? ? ? ? vrefsel bgsel1 bgsel0 cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 0000 cm1con 0654 con coe cpol ? ? ? cevt cout evpol1 evpol0 ? cref ? ? cch1 cch0 0000 cm1msksrc 0656 ? ? ? ? selsrcc3 selsrcc2 selsrcc1 selsrcc0 selsrcb3 selsrcb2 selsrcb1 selsrcb0 selsrca3 selsrca2 selsrca1 selsrca0 0000 cm1mskcon 0658 hlms ? ocen ocnen oben obnen oaen oanen nags pags acen acnen aben abnen aaen aanen 0000 cm1fltr 065a ? ? ? ? ? ? ? ? ? cfsel2 cfsel1 cfsel0 cfl tren cfdiv2 cfdiv1 cfdiv0 0000 cm2con 065c con coe cpol ? ? ? cevt cout evpol1 evpol0 ? cref ? ? cch1 cch0 0000 cm2msksrc 065e ? ? ? ? selsrcc3 selsrcc2 selsrcc1 selsrcc0 selsrcb3 selsrcb2 selsrcb1 selsrcb0 selsrca3 selsrca2 selsrca1 selsrca0 0000 cm2mskcon 0660 hlms ? ocen ocnen oben obnen oaen oanen nags pags acen acnen aben abnen aaen aanen 0000 cm2fltr 0662 ? ? ? ? ? ? ? ? ? cfsel2 cfsel1 cfsel0 cfl tren cfdiv2 cfdiv1 cfdiv0 0000 cm3con 0664 con coe cpol ? ? ? cevt cout evpol1 evpol0 ? cref ? ? cch1 cch0 0000 cm3msksrc 0666 ? ? ? ? selsrcc3 selsrcc2 selsrcc1 selsrcc0 selsrcb3 selsrcb2 selsrcb1 selsrcb0 selsrca3 selsrca2 selsrca1 selsrca0 0000 cm3mskcon 0668 hlms ? ocen ocnen oben obnen oaen oanen nags pags acen acnen aben abnen aaen aanen 0000 cm3fltr 066a ? ? ? ? ? ? ? ? ? cfsel2 cfsel1 cfsel0 cfl tren cfdiv2 cfdiv1 cfdiv0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-22: peripheral pin select input register map file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpinr0 0680 ? ? ? int1r<4:0> ? ? ? ? ? ? ? ? 1f00 rpinr1 0682 ? ? ? ? ? ? ? ? ? ? ?int2r<4:0> 001f rpinr3 0686 ? ? ?t3ckr<4:0> ? ? ?t2ckr<4:0> 1f1f rpinr4 0688 ? ? ?t5ckr<4:0> ( 1 ) ? ? ?t4ckr<4:0> ( 1 ) 1f1f rpinr7 068e ? ? ? ic2r<4:0> ? ? ? ic1r<4:0> 1f1f rpinr8 0690 ? ? ? ? ? ? ? ? ? ? ? ic3r<4:0> 001f rpinr11 0696 ? ? ? ? ? ? ? ? ? ? ?ocfar<4:0> 001f rpinr18 06a4 ? ? ? u1ctsr<4:0> ? ? ?u1rxr<4:0> 1f1f rpinr20 06a8 ? ? ?sck1r<4:0> ( 1 ) ? ? ?sdi1r<4:0> ( 1 ) 1f1f rpinr21 06aa ? ? ? ? ? ? ? ? ? ? ? ss1r<4:0> 001f legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: these bits are available in dspic33fj32(gp/mc)10x devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 68 ? 2011-2014 microchip technology inc. table 4-23: peripheral pin select output register map for dspic33fjxxgp101 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 06c0 ? ? ? rp1r<4:0> ? ? ? rp0r<4:0> 0000 rpor2 06c4 ? ? ? ? ? ? ? ? ? ? ? rp4r<4:0> 0000 rpor3 06c6 ? ? ? rp7r<4:0> ? ? ? ? ? ? ? ? 0000 rpor4 06c8 ? ? ? rp9r<4:0> ? ? ? rp8r<4:0> 0000 rpor7 06ce ? ? ?rp15r<4:0> ? ? ?rp14r<4:0> 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-24: peripheral pin select output re gister map for dspic33fjxxmc101 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 06c0 ? ? ? rp1r<4:0> ? ? ? rp0r<4:0> 0000 rpor2 06c4 ? ? ? ? ? ? ? ? ? ? ? rp4r<4:0> 0000 rpor3 06c6 ? ? ? rp7r<4:0> ? ? ? ? ? ? ? ? 0000 rpor4 06c8 ? ? ? rp9r<4:0> ? ? ? rp8r<4:0> 0000 rpor6 06cc ? ? ?rp13r<4:0> ? ? ?rp12r<4:0> 0000 rpor7 06ce ? ? ?rp15r<4:0> ? ? ?rp14r<4:0> 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-25: peripheral pin select output regi ster map for dspic33f jxx(gp/mc)102 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 06c0 ? ? ? rp1r<4:0> ? ? ? rp0r<4:0> 0000 rpor1 06c2 ? ? ? rp3r<4:0> ? ? ? rp2r<4:0> 0000 rpor2 06c4 ? ? ? rp5r<4:0> ? ? ? rp4r<4:0> 0000 rpor3 06c6 ? ? ? rp7r<4:0> ? ? ? rp6r<4:0> 0000 rpor4 06c8 ? ? ? rp9r<4:0> ? ? ? rp8r<4:0> 0000 rpor5 06ca ? ? ?rp11r<4:0> ? ? ?rp10r<4:0> 0000 rpor6 06cc ? ? ?rp13r<4:0> ? ? ?rp12r<4:0> 0000 rpor7 06ce ? ? ?rp15r<4:0> ? ? ?rp14r<4:0> 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2011-2014 microchip technology inc. ds70000652f-page 69 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 4-26: peripheral pin select output regi ster map for dspic33fj32(gp/mc)104 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 06c0 ? ? ? rp1r<4:0> ? ? ? rp0r<4:0> 0000 rpor1 06c2 ? ? ? rp3r<4:0> ? ? ? rp2r<4:0> 0000 rpor2 06c4 ? ? ? rp5r<4:0> ? ? ? rp4r<4:0> 0000 rpor3 06c6 ? ? ? rp7r<4:0> ? ? ? rp6r<4:0> 0000 rpor4 06c8 ? ? ? rp9r<4:0> ? ? ? rp8r<4:0> 0000 rpor5 06ca ? ? ?rp11r<4:0> ? ? ?rp10r<4:0> 0000 rpor6 06cc ? ? ?rp13r<4:0> ? ? ?rp12r<4:0> 0000 rpor7 06ce ? ? ?rp15r<4:0> ? ? ?rp14r<4:0> 0000 rpor8 06d0 ? ? ? rp17r<4:0> ? ? ? rp16r<4:0> 0000 rpor9 06d2 ? ? ?rp19r<4:0> ? ? ?rp18r<4:0> 0000 rpor10 06d4 ? ? ?rp21r<4:0> ? ? ?rp20r<4:0> 0000 rpor11 06d6 ? ? ?rp23r<4:0> ? ? ?rp22r<4:0> 0000 rpor12 06d8 ? ? ?rp25r<4:0> ? ? ?rp24r<4:0> 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-27: porta register map for dspic33fj16(gp/mc)101/102 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 02c0 ? ? ? ? ? ? ? ? ? ? ? trisa<4:0> 001f porta 02c2 ? ? ? ? ? ? ? ? ? ? ?ra<4:0 xxxx lata 02c4 ? ? ? ? ? ? ? ? ? ? ?lata<4:0 xxxx odca 02c6 ? ? ? ? ? ? ? ? ? ? ? odca<4:2> ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-28: porta register map for dspic33fj32(gp/mc)101/102 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 02c0 ? ? ? ? ? ? ? ? ? ? ? trisa<4:0> 001f porta 02c2 ? ? ? ? ? ? ? ? ? ? ?ra<4:0 xxxx lata 02c4 ? ? ? ? ? ? ? ? ? ? ?lata<4:0 xxxx odca 02c6 ? ? ? ? ? ? ? ? ? ? ? ? odca<3:2> ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 70 ? 2011-2014 microchip technology inc. table 4-29: porta register map for dspic33fj32(gp/mc)104 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 02c0 ? ? ? ? ? trisa<10:7> ? ?trisa<4:0> 001f porta 02c2 ? ? ? ? ? ra<10:7> ? ? ra<4:0> xxxx lata 02c4 ? ? ? ? ?lata<10:7> ? ?lata<4:0> xxxx odca 02c6 ? ? ? ? ?odca<10:7> ? ? ? odca<3:2> ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-30: portb register map for dspic33fj16gp101 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 02c8 trisb<15:14> ? ? ? ?trisb<9:7> ? ?trisb4 ? ?trisb<1:0> c393 portb 02ca rb<15:14> ? ? ? ? rb<9:7> ? ?rb4 ? ? rb<1:0> xxxx latb 02cc latb<15:14> ? ? ? ?latb<9:7> ? ?latb4 ? ?latb<1:0> xxxx odcb 02ce odcb<15:14> ? ? ? ? odcb<9:7> ? ? odcb4 ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-31: portb register map for dspic33fj16mc101 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 02c8 trisb<15:12> ? ?trisb<9:7> ? ?trisb4 ? ?trisb<1:0> f393 portb 02ca rb<15:12> ? ? rb<9:7> ? ?rb4 ? ? rb<1:0> xxxx latb 02cc latb<15:12> ? ?latb<9:7> ? ?latb4 ? ?latb<1:0> xxxx odcb 02ce odcb<15:12> ? ? odcb<9:7> ? ? odcb4 ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-32: portb register map for dspic33fj16(gp/mc)102 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 02c8 trisb<15:0> ffff portb 02ca rb<15:0> xxxx latb 02cc latb<15:0> xxxx odcb 02ce odcb<15:4> ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2011-2014 microchip technology inc. ds70000652f-page 71 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 4-33: portb register map for dspic33fj32gp101 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 02c8 trisb<15:14> ? ? ? ?trisb<9:7> ? ?trisb4 ? ?trisb<1:0> c393 portb 02ca rb<15:14> ? ? ? ? rb<9:7> ? ?rb4 ? ? rb<1:0> xxxx latb 02cc latb<15:14> ? ? ? ?latb<9:7> ? ?latb4 ? ?latb<1:0> xxxx odcb 02ce odcb<15:14> ? ? ? ? odcb<9:7> ? ? ? ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-34: portb register map for dspic33fj32mc101 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 02c8 trisb<15:12> ? ?trisb<9:7> ? ?trisb4 ? ?trisb<1:0> f393 portb 02ca rb<15:12> ? ? rb<9:7> ? ?rb4 ? ? rb<1:0> xxxx latb 02cc latb<15:12> ? ?latb<9:7> ? ?latb4 ? ?latb<1:0> xxxx odcb 02ce odcb<15:12> ? ? odcb<9:7> ? ? ? ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-35: portb register map for dspic33f j32(gp/mc)102 and dspic33fj32(gp/mc)104 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 02c8 trisb<15:0> ffff portb 02ca rb<15:0> xxxx latb 02cc latb<15:0> xxxx odcb 02ce odcb<15:5> ? ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-36: portc register map for dspic33fj32(gp/mc)104 devices file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisc 02d0 ? ? ? ? ? ?trisc<9:0> ffff portc 02d2 ? ? ? ? ? ? rc<9:0> xxxx latc 02d4 ? ? ? ? ? ?latc<9:0> xxxx odcc 02d6 ? ? ? ? ? ? odcc<9:6> ? ? ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 72 ? 2011-2014 microchip technology inc. table 4-37: system control register map file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rcon 0740 trapr iopuwr ? ? ? ? cm vregs extr swr swdten wdto sleep idle bor por xxxx ( 1 ) osccon 0742 ? cosc2 cosc1 cosc0 ? nosc2 nosc1 nosc0 clklock iolock lock ?cf ? lposcen oswen 0300 ( 2 ) clkdiv 0744 roi doze2 doze1 doze0 dozen frcdiv2 frcdiv1 frcdiv0 ? ? ? ? ? ? ? ? 3040 osctun 0748 ? ? ? ? ? ? ? ? ? ?tun<5:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: rcon register reset values are dependent on the type of reset. 2: osccon register reset values are dependent on the fosc configuration bits and by type of reset. table 4-38: nvm register map file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets nvmcon 0760 wr wren wrerr ? ? ? ? ? ? erase ? ? nvmop3 nvmop2 nvmop1 nvmop0 0000 ( 1 ) nvmkey 0766 ? ? ? ? ? ? ? ? nvmkey<7:0> 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: reset value shown is for por only. value on other reset states is dependent on the state of memory write or erase operations at the time of reset. table 4-39: pmd register map file name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0770 t5md ( 2 ) t4md ( 2 ) t3md t2md t1md ?pwm1md ( 1 ) ?i2c1md ?u1md ? spi1md ? ?ad1md 0000 pmd2 0772 ? ? ? ? ? ic3md ic2md ic1md ? ? ? ? ? ?oc2mdoc1md 0000 pmd3 0774 ? ? ? ? ? cmpmd rtccmd ? ? ? ? ? ? ? ? ? 0000 pmd4 0776 ? ? ? ? ? ? ? ? ? ? ? ? ?ctmumd ? ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this bit is available in dspic33fjxxmc10x devices only. 2: these bits are available in dspic33fj32(gp/mc)10x devices only.
? 2011-2014 microchip technology inc. ds70000652f-page 73 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 4.2.6 software stack in addition to its use as a working register, the w15 register in the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices is also used as a software stack pointer. the stack pointer always points to the first available free word and grows from lower to higher addresses. it pre-decrements for stack pops and post-increments for stack pushes, as shown in figure 4-6 . for a pc push during any call instruction, the msb of the pc is zero-extended before the push, ensuring that the msb is always clear. the stack pointer limit register (splim) associated with the stack pointer sets an upper address boundary for the stack. splim is uninitialized at reset. as is the case for the stack pointer, splim<0> is forced to ? 0 ? because all stack operations must be word-aligned. whenever an ea is generated using w15 as a source or destination pointer, the resulting address is compared with the value in splim. if the contents of the stack pointer (w15) and the splim register are equal and a push operation is performed, a stack error trap will not occur. however, the stack error trap will occur on a subsequent push operation. for example, to cause a stack error trap when the stack grows beyond address 0x0c00 in ram, initialize the splim with the value 0x0bfe. similarly, a stack pointer underflow (stack error) trap is generated when the stack pointer address is found to be less than 0x0800. this prevents the stack from interfering with the sfr space. a write to the splim register should not be immediately followed by an indirect read operation using w15. figure 4-6: call stack frame 4.2.7 data ram protection feature the dspic33f product family supports data ram protection features that enable segments of ram to be protected when used in conjunction with boot and secure code segment security. bsram (secure ram segment for bs) is accessible only from the boot segment flash code when enabled. ssram (secure ram segment for ram) is accessible only from the secure segment flash code when enabled. see table 4-1 for an overview of the bsram and ssram sfrs. 4.3 instruction addressing modes the addressing modes shown in ta b l e 4 - 4 0 form the basis of the addressing modes that are optimized to support the specific features of individual instructions. the addressing modes provided in the mac class of instructions differ from those provided in other instruction types. 4.3.1 file register instructions most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). most file register instructions employ a working register, w0, which is denoted as wreg in these instructions. the destination is typically either the same file register or wreg (with the exception of the mul instruction), which writes the result to a register or register pair. the mov instruction allows additional flexibility and can access the entire data space. 4.3.2 mcu instructions the three-operand mcu instructions are of the form: operand 3 = operand 1 operand 2 where operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as wb. operand 2 can be a w reg- ister, fetched from data memory, or a 5-bit literal. the result location can be either a w register or a data memory location. the following addressing modes are supported by mcu instructions: ? register direct ? register indirect ? register indirect post-modified ? register indirect pre-modified ? 5-bit or 10-bit literal note: a pc push during exception processing concatenates the srl register to the msb of the pc prior to the push. pc<15:0> 000000000 0 15 w15 (before call ) w15 (after call ) stack grows toward higher address 0x0000 pc<22:16> pop : [--w15] push : [w15++] note: not all instructions support all of the addressing modes given above. individual instructions can support different subsets of these addressing modes.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 74 ? 2011-2014 microchip technology inc. table 4-40: fundamental addressing modes supported 4.3.3 move and accumulator instructions move instructions and the dsp accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. in addition to the addressing modes supported by most mcu instructions, move and accumulator instructions also support register indirect with register offset addressing mode, also referred to as register indexed mode. in summary, the following addressing modes are supported by move and accumulator instructions: ? register direct ? register indirect ? register indirect post-modified ? register indirect pre-modified ? register indirect with register offset (indexed) ? register indirect with literal offset ? 8-bit literal ? 16-bit literal 4.3.4 mac instructions the dual source operand dsp instructions ( clr , ed , edac , mac , mpy , mpy.n , movsac and msc ), also referred to as mac instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables. the two-source operand prefetch registers must be members of the set {w8, w9, w10, w11}. for data reads, w8 and w9 are always directed to the x ragu, and w10 and w11 are always directed to the y agu. the effective addresses generated (before and after modification) must, therefore, be valid addresses within x data space for w8 and w9 and y data space for w10 and w11. in summary, the following addressing modes are supported by the mac class of instructions: ? register indirect ? register indirect post-modified by 2 ? register indirect post-modified by 4 ? register indirect post-modified by 6 ? register indirect with register offset (indexed) 4.3.5 other instructions in addition to the addressing modes outlined previously, some instructions use literal constants of various sizes. for example, bra (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the disi instruction uses a 14-bit unsigned literal field. in some instructions, such as add acc , the source of an operand or result is implied by the opcode itself. certain operations, such as nop , do not have any operands. addressing mode description file register direct the address of the file register is specified explicitly. register direct the contents of a register are accessed directly. register indirect the contents of wn forms the effective address (ea). register indirect post-modified the contents of wn forms the ea. wn is post-modified (incremented or decremented) by a constant value. register indirect pre-modified wn is pre-modified (incremented or decremented) by a signed constant value to form the ea. register indirect with register offset (register indexed) the sum of wn and wb forms the ea. register indirect with literal offset the sum of wn and a literal forms the ea. note: for the mov instructions, the addressing mode specified in the instruction can differ for the source and destination ea. how- ever, the 4-bit wb (register offset) field is shared by both source and destination (but typically only used by one). note: not all instructions support all the addressing modes given above. individual instructions may support different subsets of these addressing modes. note: register indirect with register offset addressing mode is available only for w9 (in x space) and w11 (in y space).
? 2011-2014 microchip technology inc. ds70000652f-page 75 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 4.4 modulo addressing modulo addressing mode is a method of providing an automated means to support circular data buffers using hardware. the objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many dsp algorithms. modulo addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). one circular buffer can be supported in each of the x (which also provides the pointers into program space) and y data spaces. modulo addressing can operate on any w register pointer. however, it is not advisable to use w14 or w15 for modulo addressing since these two registers are used as the stack frame pointer and stack pointer, respectively. in general, any particular circular buffer can be config- ured to operate in only one direction as there are certain restrictions on the buffer start address (for incre- menting buffers), or end address (for decrementing buffers), based upon the direction of the circular buffer. the only exception to the usage restrictions is for buffers that have a power-of-two length. as these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performed on both the lower and upper address boundaries). 4.4.1 start and end address the modulo addressing scheme requires that a starting and ending address be specified, and loaded into the 16-bit modulo buffer address registers: xmodsrt, xmodend, ymodsrt and ymodend (see table 4-1 ). the length of a circular buffer is not directly specified. it is determined by the difference between the correspond- ing start and end addresses. the maximum possible length of the circular buffer is 32k words (64 kbytes). 4.4.2 w address register selection ? the modulo and bit-reversed addressing control register, modcon<15:0>, contains enable flags as well as a w register field to specify the w address registers. the xwm and ywm fields select which registers will operate with modulo addressing. ? if xwm = 15, x ragu and x wagu modulo addressing is disabled. ? if ywm = 15, y agu modulo addressing is disabled. the x address space pointer w register (xwm), to which modulo addressing is to be applied, is stored in modcon<3:0> (see ta b l e 4 - 1 ). modulo addressing is enabled for x data space when xwm is set to any value other than ?15? and the xmoden bit is set at modcon<15>. the y address space pointer w register (ywm) to which modulo addressing is to be applied is stored in modcon<7:4>. modulo addressing is enabled for y data space when ywm is set to any value other than ?15? and the ymoden bit is set at modcon<14>. figure 4-7: modulo address ing operation example note: y space modulo addressing ea calcula- tions assume word-sized data (lsb of every ea is always clear). 0x1100 0x1163 start addr = 0x1100 end addr = 0x1163 length = 0x0032 words byte address mov #0x1100, w0 mov w0, xmodsrt ;set modulo start address mov #0x1163, w0 mov w0, modend ;set modulo end address mov #0x8001, w0 mov w0, modcon ;enable w1, x agu for modulo mov #0x0000, w0 ;w0 holds buffer fill value mov #0x1110, w1 ;point w1 to buffer do again, #0x31 ;fill the 50 buffer locations mov w0, [w1++] ;fill the next location again: inc w0, w0 ;increment the fill value
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 76 ? 2011-2014 microchip technology inc. 4.4.3 modulo addressing applicability modulo addressing can be applied to the effective address (ea) calculation associated with any w register. address boundaries check for addresses equal to: ? the upper boundary addresses for incrementing buffers ? the lower boundary addresses for decrementing buffers it is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). address changes can, therefore, jump beyond boundaries and still be adjusted correctly. 4.5 bit-reversed addressing bit-reversed addressing mode is intended to simplify data reordering for radix-2 fft algorithms. it is supported by the x agu for data writes only. the modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. the address source and destination are kept in normal order. thus, the only operand requiring reversal is the modifier. 4.5.1 bit-reversed addressing implementation bit-reversed addressing mode is enabled in any of these situations: ? bwm<3:0> bits (w register selection) in the modcon register are any value other than ?15? (the stack cannot be accessed using bit-reversed addressing) ? the bren bit is set in the xbrev register ? the addressing mode used is register indirect with pre-increment or post-increment if the length of a bit-reversed buffer is m = 2 n bytes, the last ?n? bits of the data buffer start address must be zeros. xb<14:0> is the bit-reversed address modifier, or ?pivot point,? which is typically a constant. in the case of an fft computation, its value is equal to half of the fft data buffer size. when enabled, bit-reversed addressing is executed only for register indirect with pre-increment or post- increment addressing and word-sized data writes. it will not function for any other addressing mode or for byte-sized data and normal addresses are generated instead. when bit-reversed addressing is active, the w address pointer is always added to the address modifier (xb) and the offset associated with the register indirect addressing mode is ignored. in addition, as word-sized data is a requirement, the lsb of the ea is ignored (and always clear). if bit-reversed addressing has already been enabled by setting the bren (xbrev<15>) bit, a write to the xbrev register should not be immediately followed by an indirect read operation using the w register that has been designated as the bit-reversed pointer. note: the modulo corrected effective address is written back to the register only when pre-modify or post-modify addressing mode is used to compute the effective address. when an address offset (such as [w7 + w2]) is used, modulo addressing correction is performed, but the contents of the register remain unchanged. note: all bit-reversed ea calculations assume word-sized data (lsb of every ea is always clear). the xb<14:0> value is scaled accordingly to generate compatible (byte) addresses. note: modulo addressing and bit-reversed addressing should not be enabled together. if an application attempts to do so, bit-reversed addressing will assume priority when active. for the x wagu and y agu, modulo addressing will be disabled. however, modulo addressing will continue to function in the x ragu.
? 2011-2014 microchip technology inc. ds70000652f-page 77 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 4-8: bit-reversed address example table 4-41: bit-reversed address sequence (16-entry) normal address bit-reversed address a3 a2 a1 a0 decimal a3 a2 a1 a0 decimal 0000 0 0000 0 0001 1 1000 8 0010 2 0100 4 0011 3 1100 12 0100 4 0010 2 0101 5 1010 10 0110 6 0110 6 0111 7 1110 14 1000 8 0001 1 1001 9 1001 9 1010 10 0101 5 1011 11 1101 13 1100 12 0011 3 1101 13 1011 11 1110 14 0111 7 1111 15 1111 15 b2 b3 b4 0 bit locations swapped left-to-right around center of binary value bit-reversed address xb<14:0> = 0x0008 for a 16-word, bit-reversed buffer b7 b6 b5 b1 b7 b6 b5 b4 b11 b10 b9 b8 b11 b10 b9 b8 b15 b14 b13 b12 b15 b14 b13 b12 sequential address pivot point b3 b2 b1 0
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 78 ? 2011-2014 microchip technology inc. 4.6 interfacing program and data memory spaces the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. the architecture is also a modified harvard scheme, meaning that data can also be present in the program space. to use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. aside from normal execution, the dspic33fj16(gp/ mc)101/102 and dspic33fj32(gp/mc)101/102/104 architecture provides two methods by which program space can be accessed during operation: ? using table instructions to access individual bytes, or words, anywhere in the program space ? remapping a portion of the program space into the data space (program space visibility) table instructions allow an application to read or write to small areas of the program memory. this capability makes the method ideal for accessing data tables that need to be updated periodically. it also allows access to all bytes of the program word. the remapping method allows an application to access a large block of data on a read-only basis, which is ideal for lookups from a large table of static data. the application can only access the lsw of the program word. 4.6.1 addressing program space since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. the solution depends on the interface method to be used. for table operations, the 8-bit table page (tblpag) register is used to define a 32k word region within the program space. this is concatenated with a 16-bit ea to arrive at a full 24-bit program space address. in this format, the msb of tblpag is used to determine if the operation occurs in the user memory (tblpag<7> = 0 ) or the configuration memory (tblpag<7> = 1 ). for remapping operations, the 8-bit program space visibility (psvpag) register is used to define a 16k word page in the program space. when the msb of the ea is ? 1 ?, psvpag is concatenated with the lower 15 bits of the ea to form a 23-bit program space address. unlike table operations, this limits remapping operations strictly to the user memory area. table 4-42 and figure 4-9 show how the program ea is created for table operations and remapping accesses from the data ea. table 4-42: program space address construction access type access space program space address <23> <22:16> <15> <14:1> <0> instruction access (code execution) user 0 pc<22:1> 0 0xx xxxx xxxx xxxx xxxx xxx0 tblrd/tblwt (byte/word read/write) user tblpag<7:0> data ea<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx configuration tblpag<7:0> data ea<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx program space visibility (block remap/read) user 0 psvpag<7:0> data ea<14:0> ( 1 ) 0 xxxx xxxx xxx xxxx xxxx xxxx note 1: data ea<15> is always ? 1 ? in this case, but is not used in calculating the program space address. bit 15 of the address is psvpag<0>.
? 2011-2014 microchip technology inc. ds70000652f-page 79 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 4-9: data access from program space address generation 0 program counter 23 bits 1 psvpag 8 bits ea 15 bits program counter (1) select tblpag 8 bits ea 16 bits byte select 0 0 1/0 user/configuration table operations (2) program space visibility (1) space select 24 bits 23 bits (remapping) 1/0 0 note 1: the least significant bit of program space addresses is always fixed as ? 0 ? to maintain word alignment of data in the program and data spaces. 2: table operations are not required to be word-aligned. table read operations are permitted in the configuration memory space.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 80 ? 2011-2014 microchip technology inc. 4.6.2 data access from program memory using table instructions the tblrdl and tblwtl instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. the tblrdh and tblwth instructions are the only method to read or write the upper 8 bits of a program space word as data. the pc is incremented by two for each successive 24-bit program word. this allows program memory addresses to directly map to data space addresses. pro- gram memory can thus be regarded as two 16-bit-wide word address spaces, residing side by side, each with the same address range. tblrdl and tblwtl access the space that contains the least significant data word. tblrdh and tblwth access the space that contains the upper data byte. two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. both function as either byte or word operations. ? tblrdl (table read low): - in word mode, this instruction maps the lower word of the program space location (p<15:0>) to a data address (d<15:0>). - in byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. the upper byte is selected when byte select is ? 1 ?; the lower byte is selected when it is ? 0 ?. ? tblrdh (table read high): - in word mode, this instruction maps the entire upper word of a program address (p<23:16>) to a data address. note that d<15:8>, the ?phantom byte?, will always be ? 0 ?. - in byte mode, this instruction maps the upper or lower byte of the program word to d<7:0> of the data address, in the tblrdl instruc- tion. the data is always ? 0 ? when the upper ?phantom? byte is selected (byte select = 1 ). in a similar fashion, two table instructions, tblwth and tblwtl , are used to write individual bytes or words to a program space address. the details of their operation are explained in section 5.0 ?flash program memory? . for all table operations, the area of program memory space to be accessed is determined by the table page register (tblpag). tblpag covers the entire program memory space of the device, including user and configuration spaces. when tblpag<7> = 0 , the table page is located in the user memory space. when tblpag<7> = 1 , the page is located in configuration space. figure 4-10: accessing program memory with table instructions 0 8 16 23 00000000 00000000 00000000 00000000 ?phantom? byte tblrdh.b (wn<0> = 0 ) tblrdl.w tblrdl.b (wn<0> = 1 ) tblrdl.b (wn<0> = 0 ) 23 15 0 tblpag 02 0x000000 0x800000 0x020000 0x030000 program space the address for the table operation is determined by the data ea within the page defined by the tblpag register. only read operations are shown; write operations are also valid in the user memory area.
? 2011-2014 microchip technology inc. ds70000652f-page 81 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 4.6.3 reading data from program memory using program space visibility the upper 32 kbytes of data space may optionally be mapped into any 16k word page of the program space. this option provides transparent access to stored constant data from the data space without the need to use special instructions (such as tblrdl and tblrdh ). program space access through the data space occurs if the msb of the data space ea is ? 1 ? and program space visibility is enabled by setting the psv bit in the core control register (corcon<2>). the location of the program memory space to be mapped into the data space is determined by the program space visibility page register (psvpag). this 8-bit register defines any one of 256 possible pages of 16k words in program space. in effect, psvpag functions as the upper 8 bits of the program memory address, with the 15 bits of the ea functioning as the lower bits. by incrementing the pc by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required. although each data space address, 0x8000 and higher, maps directly into a corresponding program memory address (see figure 4-11), only the lower 16 bits of the 24-bit program word are used to contain the data. the upper 8 bits of any program space location used as data should be programmed with ? 1111 1111 ? or ? 0000 0000 ? to force a nop . this prevents possible issues should the area of code ever be accidentally executed. for operations that use psv and are executed outside a repeat loop, the mov and mov.d instructions require one instruction cycle in addition to the specified execution time. all other instructions require two instruction cycles in addition to the specified execution time. for operations that use psv, and are executed inside a repeat loop, these instances require two instruction cycles in addition to the specified execution time of the instruction: ? execution in the first iteration ? execution in the last iteration ? execution prior to exiting the loop due to an interrupt ? execution upon re-entering the loop after an interrupt is serviced any other iteration of the repeat loop will allow the instruction using psv to access data, to execute in a single cycle. figure 4-11: program space visibility operation note: psv access is temporarily disabled during table reads/writes. 23 15 0 psvpag data space program space 0x0000 0x8000 0xffff 02 0x000000 0x800000 0x010000 0x018000 when corcon<2> = 1 and ea<15> = 1 : the data in the page designated by psvpag is mapped into the upper half of the data memory space... data ea<14:0> ...while the lower 15 bits of the ea specify an exact address within the psv area. this corresponds exactly to the same lower 15 bits of the actual program space address. psv area
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 82 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 83 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 5.0 flash program memory the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices contain internal flash program memory for storing and executing application code. the memory is readable, writable and erasable during normal operation over the entire v dd range. flash memory can be programmed in two ways: ? in-circuit serial programming? (icsp?) programming capability ? run-time self-programming (rtsp) icsp allows a device to be serially programmed while in the end application circuit. this is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: pgecx/pgedx), and three other lines for power (v dd ), ground (v ss ) and master clear (mclr ). this allows users to manufac- ture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. rtsp is accomplished using tblrd (table read) and tblwt (table write) instructions. with rtsp, the user application can write program memory data in a single program memory word and erase program memory in blocks or ?pages? of 512 instructions (1536 bytes). 5.1 table instructions and flash programming regardless of the method used, all programming of flash memory is done with the table read and table write instructions. these allow direct read and write access to the program memory space, from the data memory, while the device is in normal operating mode. the 24-bit target address in the program memory is formed using bits<7:0> of the tblpag register and the effective address (ea) from a w register specified in the table instruction, as shown in figure 5-1 . the tblrdl and the tblwtl instructions are used to read or write to bits<15:0> of program memory. tblrdl and tblwtl can access program memory in both word and byte modes. the tblrdh and tblwth instructions are used to read or write to bits<23:16> of program memory. tblrdh and tblwth can also access program memory in word or byte mode. figure 5-1: addressing for table registers note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to ?flash programming? (ds70191) in the ?dspic33/pic24 family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. 0 program counter 24 bits program counter tblpag reg 8 bits working reg ea 16 bits byte 24-bit ea 0 1/0 select using table instruction using user/configuration space select
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 84 ? 2011-2014 microchip technology inc. 5.2 rtsp operation the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 flash program memory array is organized into rows of 64 instructions or 192 bytes. rtsp allows the user application to erase a page of memory, which consists of eight rows (512 instructions); and to program one word. table 26-12 shows typical erase and programming times. the 8-row erase pages are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes. 5.3 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. the processor stalls (waits) until the operation is finished. the programming time depends on the frc accuracy (see table 26-18 ) and the value of the frc oscillator tuning register (see register 8-3 ). use the following formula to calculate the minimum and maximum values for the word write time and page erase time (see parameters d138a and d138b , and parameters d137a and d137b in table 26-12 , respectively). equation 5-1: programming time for example, if the device is operating at +125c, the frc accuracy will be 2%. if the tun<5:0> bits (see register 8-3 ) are set to ?b000000 , the minimum row write time is equal to equation 5-2 . equation 5-2: minimum row write time the maximum row write time is equal to equation 5-3 . equation 5-3: maximum row write time setting the wr bit (nvmcon<15>) starts the opera- tion and the wr bit is automatically cleared when the operation is finished. 5.3.1 programming algorithm for flash program memory programmers can program one word (24 bits) of program flash memory at a time. to do this, it is necessary to erase the 8-row erase page that contains the desired address of the location the user wants to change. for protection against accidental operations, the write initiate sequence for nvmkey must be used to allow any erase or program operation to proceed. after the programming command has been executed, the user application must wait for the programming time until programming is complete. the two instructions following the start of the programming sequence should be nop s. refer to ?flash programming? (ds70191) in the ?dspic33/pic24 family reference manual? for details and codes examples on programming using rtsp. 5.4 control registers two sfrs are used to read and write the program flash memory: nvmcon and nvmkey. the nvmcon register ( register 5-1 ) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. nvmkey is a write-only register that is used for write protection. to start a pr ogramming or erase sequence, the user application must consecutively write 0x55 and 0xaa to the nvmkey register. refer to section 5.3 ?programming operations? for further details. t 7.37 mhz frc accuracy ?? % frc tuning ?? % ? ? ------------------------------------------------------------------------------------------------------------------------- - t rw 355 cycles 7.37 mhz 10.02 + ?? 1 0.00375 ? ?? ? ? ---------------------------------------------------------------------------------------------- 47.4 ? s = = t rw 355 cycles 7.37 mhz 10.02 ? ?? 1 0.00375 ? ?? ? ? --------------------------------------------------------------------------------------------- - 49.3 ? s = = note: performing a page erase operation on the last page of program memory will clear the flash configuration words, thereby enabling code protection as a result. therefore, users should avoid performing page erase operations on the last page of program memory.
? 2011-2014 microchip technology inc. ds70000652f-page 85 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 5-2: nvmkey: nonvol atile memory key register register 5-1: nvmcon: flash memory control register r/so-0 ( 1 ) r/w-0 ( 1 ) r/w-0 ( 1 ) u-0 u-0 u-0 u-0 u-0 wr wren wrerr ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 ( 1 ) u-0 u-0 r/w-0 ( 1 ) r/w-0 ( 1 ) r/w-0 ( 1 ) r/w-0 ( 1 ) ? erase ? ?nvmop3 ( 2 ) nvmop2 ( 2 ) nvmop1 ( 2 ) nvmop0 ( 2 ) bit 7 bit 0 legend: so = settable only bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 wr: write control bit ( 1 ) 1 = initiates a flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once operation is complete 0 = program or erase operation is complete and inactive bit 14 wren: write enable bit ( 1 ) 1 = enables flash program/erase operations 0 = inhibits flash program/erase operations bit 13 wrerr: write sequence error flag bit ( 1 ) 1 = an improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the wr bit) 0 = the program or erase operation completed normally bit 12-7 unimplemented: read as ? 0 ? bit 6 erase: erase/program enable bit ( 1 ) 1 = performs the erase operation specified by nvmop<3:0> on the next wr command 0 = performs the program operation specified by nvmop<3:0> on the next wr command bit 5-4 unimplemented: read as ? 0 ? bit 3-0 nvmop<3:0>: nvm operation selection bits ( 1 , 2 ) if erase = 1 : 1111 = no operation 1101 = erase general segment 1100 = no operation 0011 = no operation 0010 = memory page erase operation 0001 = no operation 0000 = no operation if erase = 0 : 1111 = no operation 1101 = no operation 1100 = no operation 0011 = memory word program operation 0010 = no operation 0001 = no operation 0000 = no operation note 1: these bits can only be reset on a por. 2: all other combinations of nvmop<3:0> are unimplemented. u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ?
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 86 ? 2011-2014 microchip technology inc. bit 15 bit 8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-0 nvmkey<7:0>: key register bits (write-only)
? 2011-2014 microchip technology inc. ds70000652f-page 87 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 6.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst . the following is a list of device reset sources: ? por: power-on reset ? bor: brown-out reset ?mclr : master clear pin reset ?swr: reset instruction ? wdto: watchdog timer reset ? cm: configuration mismatch reset ? trapr: trap conflict reset ? iopuwr: illegal condition device reset - illegal opcode reset - uninitialized w register reset - security reset a simplified block diagram of the reset module is shown in figure 6-1 . any active source of reset will make the sysrst sig- nal active. on system reset, some of the registers associated with the cpu and peripherals are forced to a known reset state, and some are unaffected. all types of device reset set a corresponding status bit in the rcon register to indicate the type of reset (see register 6-1 ). all bits that are set, with the exception of the por bit (rcon<0>), are cleared during a por event. the user application can set or clear any bit at any time during code execution. the rcon bits only serve as status bits. setting a particular reset status bit in software does not cause a device reset to occur. the rcon register also has other bits associated with the watchdog timer and device power-saving states. the function of these bits is discussed in other sections of this data sheet. figure 6-1: reset sy stem block diagram note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to ?reset? (ds70192) in the ? dspic33/pic24 family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. note: refer to the specific peripheral section or section 3.0 ?cpu? of this data sheet for register reset states. note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset is meaningful. mclr v dd bor sleep or idle reset instruction wdt module glitch filter trap conflict illegal opcode uninitialized w register sysrst v dd rise detect por configuration mismatch internal regulator
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 88 ? 2011-2014 microchip technology inc. 6.1 reset control register register 6-1: rcon: re set control register ( 1 ) r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 trapr iopuwr ? ? ? ?cmvregs bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 extr swr swdten ( 2 ) wdto sleep idle bor por bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 trapr: trap reset flag bit 1 = a trap conflict reset has occurred 0 = a trap conflict reset has not occurred bit 14 iopuwr: illegal opcode or uninitialized w access reset flag bit 1 = an illegal opcode detection, an illegal address mode or uninitialized w register used as an address pointer caused a reset 0 = an illegal opcode or uninitialized w reset has not occurred bit 13-10 unimplemented: read as ? 0 ? bit 9 cm: configuration mismatch flag bit 1 = a configuration mismatch reset has occurred 0 = a configuration mismatch reset has not occurred bit 8 vregs: voltage regulator stand-by during sleep bit 1 = voltage regulator is active during sleep 0 = voltage regulator goes into stand-by mode during sleep bit 7 extr: external reset (mclr ) pin bit 1 = a master clear (pin) reset has occurred 0 = a master clear (pin) reset has not occurred bit 6 swr: software reset (instruction) flag bit 1 = a reset instruction has been executed 0 = a reset instruction has not been executed bit 5 swdten: software enable/disable of wdt bit ( 2 ) 1 = wdt is enabled 0 = wdt is disabled bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred bit 3 sleep: wake-up from sleep flag bit 1 = device has been in sleep mode 0 = device has not been in sleep mode note 1: all of the reset status bits can be set or cleared in software. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is set to ? 1 ? (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting.
? 2011-2014 microchip technology inc. ds70000652f-page 89 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 bit 2 idle: wake-up from idle flag bit 1 = device has been in idle mode 0 = device has not been in idle mode bit 1 bor: brown-out reset flag bit 1 = a brown-out reset has occurred 0 = a brown-out reset has not occurred bit 0 por: power-on reset flag bit 1 = a power-on reset has occurred 0 = a power-on reset has not occurred register 6-1: rcon: re set control register ( 1 ) (continued) note 1: all of the reset status bits can be set or cleared in software. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is set to ? 1 ? (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 90 ? 2011-2014 microchip technology inc. 6.2 system reset the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family of devices have two types of reset: ?cold reset ?warm reset a cold reset is the result of a por or a bor. on a cold reset, the fnosc<2:0> configuration bits in the foscsel configuration register selects the device clock source. a warm reset is the result of all other reset sources, including the reset instruction. on warm reset, the device will continue to operate from the current clock source as indicated by the current oscillator selec- tion (cosc<2:0>) bits in the oscillator control (osccon<14:12>) register. the device is kept in a reset state until the system power supplies have stabilized at appropriate levels and the oscillator clock is ready. the sequence in which this occurs is shown in figure 6-2 . table 6-1: oscillator delay oscillator mode oscillator start-up delay oscillator start-up timer pll lock time total delay frc, frcdiv16, frcdivn t oscd ( 1 ) ?? t oscd frcpll t oscd ( 1 ) ?t lock ( 3 ) t oscd ( 1 ) + t lock ( 3 ) ms t oscd ( 1 ) t ost ( 2 ) ?t oscd ( 1 ) + t ost ( 2 ) hs t oscd ( 1 ) t ost ( 2 ) ?t oscd ( 1 ) + t ost ( 2 ) ec ? ? ? ? mspll t oscd ( 1 ) t ost ( 2 ) t lock ( 3 ) t oscd ( 1 ) + t ost ( 2 ) + t lock ( 3 ) ecpll ? ? t lock ( 3 ) t lock ( 3 ) sosc t oscd ( 1 ) t ost ( 2 ) ?t oscd ( 1 ) + t ost ( 2 ) lprc t oscd ( 1 ) ?? t oscd ( 1 ) note 1: t oscd = oscillator start-up delay (1.1 ? s max. for frc, 70 ? s max. for lprc). crystal oscillator start-up times vary with crystal characteristics, load capacitance, etc. 2: t ost = oscillator start-up timer delay (1024 oscillator clock period). for example, t ost = 102.4 ? s for a 10 mhz crystal and t ost = 32 ms for a 32 khz crystal. 3: t lock = pll lock time (1.5 ms nominal) if pll is enabled.
? 2011-2014 microchip technology inc. ds70000652f-page 91 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 6-2: system reset timing reset run device status v dd v por v bor por bor sysrst t pwrt t por t bor oscillator clock t oscd t ost t lock time fscm t fscm 1 2 3 4 5 6 1. por: a por circuit holds the device in reset when the power supply is turned on. the por circuit is active until v dd crosses the v por threshold and the delay, t por , has elapsed. 2. bor: the on-chip voltage regulator has a bor circuit that keeps the device in reset until v dd crosses the v bor threshold and the delay, t bor , has elapsed. the delay, t bor , ensures the voltage regulator output becomes stable. 3. pwrt timer: the power-up timer continues to hold the processor in reset for a specific period of time (t pwrt ) after a bor. the delay, t pwrt , ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. after the delay, t pwrt , has elapsed, the sysrst becomes inactive, which in turn, enables the selected oscillator to start generating clock cycles. 4. oscillator delay: the total delay for the clock to be ready for various clock source selections is given in ta b l e 6 - 1 . refer to section 8.0 ?oscillator configuration? for more information. 5. when the oscillator clock is ready, the processor begins execution from location, 0x000000. the user application programs a goto instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6. the fail-safe clock monitor (fscm), if enabled, begins to monitor the system clock when the system clock is ready and the delay , t fscm , has elapsed. table 6-2: oscillator parameters symbol parameter value v por por threshold 1.8v nominal t por por extension time 30 ? s maximum v bor bor threshold 2.5v nominal t bor bor extension time 100 ? s maximum t pwrt power-up time delay 64 ms nominal t fscm fail-safe clock monitor delay 900 ? s maximum note: when the device exits the reset condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges; otherwise, the device may not function correctly. the user appli- cation must ensure that the delay between the time power is first applied, and the time sysrst becomes inactive, is long enough to get all operating parameters within specification.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 92 ? 2011-2014 microchip technology inc. 6.3 por a por circuit ensures the device is reset from power- on. the por circuit is active until v dd crosses the v por threshold and the delay, t por , has elapsed. the delay, t por , ensures that the internal device bias circuits become stable. the device supply voltage characteristics must meet the specified starting voltage and rise rate require- ments to generate the por. refer to section 26.0 ?electrical characteristics? for details. the power-on reset (por) status bit in the reset con- trol (rcon<0>) register is set to indicate the power-on reset. 6.4 bor and pwrt the on-chip regulator has a bor circuit that resets the device when the v dd is too low (v dd < v bor ) for proper device operation. the bor circuit keeps the device in reset until v dd crosses the v bor threshold and the delay, t bor , has elapsed. the delay, t bor , ensures the voltage regulator output becomes stable. the brown-out reset (bor) status bit in the reset control (rcon<1>) register is set to indicate the brown-out reset. the device will not run at full speed after a bor as the v dd should rise to acceptable levels for full-speed operation. the power-up timer (pwrt) provides power- up time delay (t pwrt ) to ensure that the system power supplies have stabilized at the appropriate levels for full-speed operation before the sysrst is released. refer to section 23.0 ?special features? for further details. figure 6-3 shows the typical brown-out scenarios. the reset delay (t bor + t pwrt ) is initiated each time v dd rises above the v bor trip point. figure 6-3: brown-out reset situations v dd sysrst v bor v dd sysrst v bor v dd sysrst v bor t bor + t pwrt v dd dips before pwrt expires t bor + t pwrt t bor + t pwrt
? 2011-2014 microchip technology inc. ds70000652f-page 93 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 6.5 external reset (extr) the external reset is generated by driving the mclr pin low. the mclr pin is a schmitt trigger input with an additional glitch filter. reset pulses that are longer than the minimum pulse width will generate a reset. refer to section 26.0 ?electrical characteristics? for minimum pulse-width specifications. the external reset pin (mclr ) bit (extr) in the reset control (rcon) register is set to indicate the mclr reset. 6.5.1 external supervisory circuit many systems have external supervisory circuits that generate reset signals to reset multiple devices in the system. this external reset signal can be directly connected to the mclr pin to reset the device when the rest of the system is reset. 6.5.2 internal supervisory circuit when using the internal power supervisory circuit to reset the device, the external reset pin (mclr ) should be tied directly or resistively to v dd . in this case, the mclr pin will not be used to generate a reset. the external reset pin (mclr ) does not have an internal pull-up and must not be left unconnected. 6.6 software reset instruction (swr) whenever the reset instruction is executed, the device will assert sysrst , placing the device in a special reset state. this reset state will not re-initialize the clock. the clock source in effect prior to the reset instruction will remain as the source. sysrst is released at the next instruction cycle and the reset vector fetch will commence. the software reset (instruction) flag (swr) bit in the reset control (rcon<6>) register is set to indicate the software reset. 6.7 watchdog timer time-out reset (wdto) whenever a watchdog timer time-out reset occurs, the device will asynchronously assert sysrst . the clock source will remain unchanged. a wdt time-out during sleep or idle mode will wake-up the processor, but will not reset the processor. the watchdog timer time-out flag (wdto) bit in the reset control (rcon<4>) register is set to indicate the watchdog timer reset. refer to section 23.4 ?watchdog timer (wdt)? for more information on the watchdog timer reset. 6.8 trap conflict reset if a lower priority hard trap occurs while a higher priority trap is being processed, a hard trap conflict reset occurs. the hard traps include exceptions of priority level 13 through level 15, inclusive. the address error (level 13) and oscillator error (level 14) traps fall into this category. the trap reset flag (trapr) bit in the reset control (rcon<15>) register is set to indicate the trap conflict reset. refer to section 7.0 ?interrupt controller? for more information on trap conflict resets. 6.9 configuration mismatch reset to maintain the integrity of the peripheral pin select control registers, they are constantly monitored with shadow registers in hardware. if an unexpected change in any of the registers occurs (such as cell disturbances caused by esd or other external events), a configuration mismatch reset occurs. the configuration mismatch flag (cm) bit in the reset control (rcon<9>) register is set to indicate the configuration mismatch reset. refer to section 10.0 ?i/o ports? for more information on the configuration mismatch reset. 6.10 illegal condition device reset an illegal condition device reset occurs due to the following sources: ? illegal opcode reset ? uninitialized w register reset ? security reset the illegal opcode or uninitialized w access reset flag (iopuwr) bit in the reset control (rcon<14>) register is set to indicate the illegal condition device reset. 6.10.1 illegal opcode reset a device reset is generated if the device attempts to execute an illegal opcode value that is fetched from program memory. the illegal opcode reset function can prevent the device from executing program memory sections that are used to store constant data. to take advantage of the illegal opcode reset, use only the lower 16 bits of each program memory section to store the data values. the upper 8 bits should be programmed with 0x3f, which is an illegal opcode value. note: the configuration mismatch feature and associated reset flag is not available on all devices.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 94 ? 2011-2014 microchip technology inc. 6.10.2 uninitialized w register reset any attempts to use the uninitialized w register as an address pointer will reset the device. the w register array (with the exception of w15) is cleared during all resets and is considered uninitialized until written to. 6.10.3 security reset if a program flow change (pfc) or vector flow change (vfc) targets a restricted location in a protected segment (boot and secure segment), that operation will cause a security reset. the pfc occurs when the program counter is reloaded as a result of a call, jump, computed jump, return, return from subroutine or other form of branch instruction. the vfc occurs when the program counter is reloaded with an interrupt or trap vector. 6.11 using the rcon status bits the user application can read the reset control (rcon) register after any device reset to determine the cause of the reset. table 6-3 provides a summary of reset flag bit operation. table 6-3: reset flag bit operation note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset will be meaningful. flag bit set by: cleared by: trapr (rcon<15>) trap conflict event por, bor iopwr (rcon<14>) illegal opcode or uninitialized w register access or security reset por, bor cm (rcon<9>) configuration mismatch por, bor extr (rcon<7>) mclr reset por swr (rcon<6>) reset instruction por, bor wdto (rcon<4>) wdt time-out pwrsav instruction, clrwdt instruction, por, bor sleep (rcon<3>) pwrsav #sleep instruction por, bor idle (rcon<2>) pwrsav #idle instruction por, bor bor (rcon<1>) por, bor ? por (rcon<0>) por ? note: all reset flag bits can be set or cleared by user software.
? 2011-2014 microchip technology inc. ds70000652f-page 95 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 7.0 interrupt controller the interrupt controller reduces the numerous periph- eral interrupt request signals to a single interrupt request signal to the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family cpu. it has the following features: ? up to eight processor exceptions and software traps ? seven user-selectable priority levels ? interrupt vector table (ivt) with up to 118 vectors ? a unique vector for each interrupt or exception source ? fixed priority within a specified user priority level ? alternate interrupt vector table (aivt) for debug support ? fixed interrupt entry and return latencies 7.1 interrupt vector table the interrupt vector table (ivt) is shown in figure 7-1 . the ivt resides in program memory, starting at location, 000004h. the ivt contains 126 vectors consisting of eight non-maskable trap vectors, plus up to 118 sources of interrupt. in general, each interrupt source has its own vector. each interrupt vector contains a 24-bit-wide address. the value programmed into each interrupt vector location is the starting address of the associated interrupt service routine (isr). interrupt vectors are prioritized in terms of their natural priority. this priority is linked to their position in the vector table. lower addresses generally have a higher natural priority. for example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/ mc)101/102/104 devices implement up to 26 unique interrupts and 4 nonmaskable traps. these are summarized in ta b l e 7 - 1 and tab l e 7 - 2 . 7.1.1 alternate interrupt vector ta b l e the alternate interrupt vector table (aivt) is located after the ivt, as shown in figure 7-1 . access to the aivt is provided by the altivt control bit (intcon2<15>). if the altivt bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. the altern ate vectors are organized in the same manner as the default vectors. the aivt supports debugging by providing a way to switch between an application and a support environ- ment without requiring the interrupt vectors to be reprogrammed. this feature also enables switching between applications to facilitate evaluation of different software algorithms at run time. if the aivt is not needed, the aivt should be programmed with the same addresses used in the ivt. 7.2 reset sequence a device reset is not a true exception because the inter- rupt controller is not involved in the reset process. the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/ mc)101/102/104 devices clear their registers in response to a reset, forcing the pc to zero. the digital signal controller then begins program execution at location, 0x000000. a goto instruction at the reset address can redirect program execution to the appropriate start-up routine. note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a compre- hensive reference source. to complement the information in this data sheet, refer to ?interrupts (part iv)? (ds70300) in the ? dspic33/pic24 family reference man- ual? , which is available on the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. note: any unimplemented or unused vector locations in the ivt and aivt should be programmed with the address of a default interrupt handler routine that contains a reset instruction.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 96 ? 2011-2014 microchip technology inc. figure 7-1: dspic33fj16(gp/mc)101/ 102 and dspic33fj32(gp/mc)101/102/104 interrupt vector table reset ? goto instruction 0x000000 reset ? goto address 0x000002 reserved 0x000004 oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 0x000014 interrupt vector 1 ~ ~ ~ interrupt vector 52 0x00007c interrupt vector 53 0x00007e interrupt vector 54 0x000080 ~ ~ ~ interrupt vector 116 0x0000fc interrupt vector 117 0x0000fe reserved 0x000100 reserved 0x000102 reserved oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 0x000114 interrupt vector 1 ~ ~ ~ interrupt vector 52 0x00017c interrupt vector 53 0x00017e interrupt vector 54 0x000180 ~ ~ ~ interrupt vector 116 interrupt vector 117 0x0001fe start of code 0x000200 decreasing natural order priority interrupt vector table (ivt) (1) alternate interrupt vector table (aivt) (1) note 1: see table 7-1 for the list of implemented interrupt vectors.
? 2011-2014 microchip technology inc. ds70000652f-page 97 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 7-1: interrupt vectors vector number interrupt request (irq) number ivt address aivt address interrupt source 8 0 0x000014 0x000114 int0 ? external interrupt 0 9 1 0x000016 0x000116 ic1 ? input capture 1 10 2 0x000018 0x000118 oc1 ? output compare 1 11 3 0x00001a 0x00011a t1 ? timer1 12 4 0x00001c 0x00011c reserved 13 5 0x00001e 0x00011e ic2 ? input capture 2 14 6 0x000020 0x000120 oc2 ? output compare 2 15 7 0x000022 0x000122 t2 ? timer2 16 8 0x000024 0x000124 t3 ? timer3 17 9 0x000026 0x000126 spi1e ? spi1 error 18 10 0x000028 0x000128 spi1 ? spi1 transfer done 19 11 0x00002a 0x00012a u1rx ? uart1 receiver 20 12 0x00002c 0x00012c u1tx ? uart1 transmitter 21 13 0x00002e 0x00012e adc1 ? adc1 22-23 14-15 0x000030-0x000032 0x000130-0x000132 reserved 24 16 0x000034 0x000134 si2c1 ? i2c1 slave events 25 17 0x000036 0x000136 mi2c1 ? i2c1 master events 26 18 0x000038 0x000138 cmp ? comparator interrupt 27 19 0x00003a 0x00013a change notification interrupt 28 20 0x00003c 0x00013c int1 ? external interrupt 1 29-34 21-26 0x00003e-0x000038 0x00013e-0x000138 reserved 35 27 0x00004a 0x00014a t4 ? timer4 ( 2 ) 36 28 0x00004c 0x00014c t5 ? timer5 ( 2 ) 37 29 0x00004e 0x00014e int2 ? external interrupt 2 38-44 30-36 0x000050-0x00005c 0x000150-0x00015c reserved 45 37 0x00005e 0x00015e ic3 ? input capture 3 46-64 38-56 0x000060-0x000084 0x000160-0x000184 reserved 65 57 0x000086 0x000186 pwm1 ? pwm1 period match ( 1 ) 66-69 58-61 0x000088-0x00008e 0x000188-0x00018e reserved 70 62 0x000090 0x000190 rtcc ? real-time clock and calendar 71 63 0x000092 0x000192 flta1 ? pwm1 fault a ( 1 ) 72 64 0x000094 0x000194 fltb1 ? pwm1 fault b ( 3 ) 73 65 0x000096 0x000196 u1e ? uart1 error 74-84 66-76 0x000098-0x0000ac 0x000198-0x0001ac reserved 85 77 0x0000ae 0x0001ae ctmu ? charge time measurement unit 86-125 78-117 0x0000b0-0x0000fe 0x0001b0-0x0001fe reserved note 1: this interrupt vector is available in dspic33fj(16/32)mc10x devices only. 2: this interrupt vector is available in dspic33fj32(gp/mc)10x devices only. 3: this interrupt vector is available in dspic33fj(16/32)mc102/104 devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 98 ? 2011-2014 microchip technology inc. table 7-2: trap vectors 7.3 interrupt control and status registers the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices implement a total of 26 registers for the interrupt controller: ? intcon1 ? intcon2 ?ifsx ?iecx ?ipcx ?inttreg 7.3.1 intcon1 and intcon2 global interrupt functions are controlled from intcon1 and intcon2. intcon1 contains the interrupt nest- ing disable (nstdis) bit as well as the control and status flags for the processor trap sources. the intcon2 register controls the external interrupt request signal behavior and the use of the alternate interrupt vector table. 7.3.2 ifsx registers the ifsx registers maintain all of the interrupt request flags. each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software. 7.3.3 iecx registers the iecx registers maintain all of the interrupt enable bits. these control bits are used to individually enable interrupts from the peripherals or external signals. 7.3.4 ipcx registers the ipcx registers are used to set the interrupt priority level (ipl) for each source of interrupt. each user interrupt source can be assigned to one of eight priority levels. 7.3.5 inttreg the inttreg register contains the associated interrupt vector number and the new cpu interrupt priority level, which are latched into vector number (vecnum<6:0>) and interrupt level (ilr<3:0>) bit fields in the inttreg register. the new interrupt priority level is the priority of the pending interrupt. the interrupt sources are assigned to the ifsx, iecx and ipcx registers in the same sequence that they are listed in table 7-1 . for example, the int0 (external interrupt 0) is shown as having vector number 8 and a natural order priority of 0. thus, the int0if bit is found in ifs0<0>, the int0ie bit in iec0<0> and the int0ipx bits in the first positions of ipc0 (ipc0<2:0>). 7.3.6 status/control registers although they are not specifically part of the interrupt control hardware, two of the cpu control registers contain bits that control interrupt functionality. ? the cpu status register, sr, contains the ipl<2:0> bits (sr<7:5>). these bits indicate the current cpu interrupt priority level. the user application can change the current cpu interrupt priority level by writing to the iplx bits. ? the corcon register contains the ipl3 bit which, together with ipl<2:0>, also indicates the current cpu interrupt priority level. ipl3 is a read-only bit so that trap events cannot be masked by the user software. all interrupt registers are described in register 7-1 through register 7-28 on the following pages. vector number ivt addres s aivt address trap source 0 0x000004 0x000104 reserved 1 0x000006 0x000106 oscillator failure 2 0x000008 0x000108 address error 3 0x00000a 0x00010a stack error 4 0x00000c 0x00010c math error 5 0x00000e 0x00010e reserved 6 0x000010 0x000110 reserved 7 0x000012 0x000112 reserved
? 2011-2014 microchip technology inc. ds70000652f-page 99 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 7-1: sr: cpu status register ( 1 ) r-0 r-0 r/c-0 r/c-0 r-0 r/c-0 r-0 r/w-0 oa ob sa sb oab sab da dc bit 15 bit 8 r/w-0 ( 3 ) r/w-0 ( 3 ) r/w-0 ( 3 ) r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl2 ( 2 ) ipl1 ( 2 ) ipl0 ( 2 ) ra n ov z c bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 ipl<2:0>: cpu interrupt priority level status bits ( 2 , 3 ) 111 = cpu interrupt priority level is 7 (15); user interrupts are disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) note 1: for complete register details, see register 3-1 . 2: the ipl<2:0> bits are concatenated with the ipl<3> bit (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read-only when nstdis (intcon1<15>) = 1 . register 7-2: corcon: core control register ( 1 ) u-0 u-0 u-0 r/w-0 r/w-0 r-0 r-0 r-0 ? ? ? us edt dl2 dl1 dl0 bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-0 r/c-0 r/w-0 r/w-0 r/w-0 sata satb satdw accsat ipl3 ( 2 ) psv rnd if bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 3 ipl3: cpu interrupt priority level status bit 3 ( 2 ) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less note 1: for complete register details, see register 3-2 . 2: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 100 ? 2011-2014 microchip technology inc. register 7-3: intcon1: in terrupt control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 sftacerr div0err ? matherr addrerr stkerr oscfail ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 nstdis: interrupt nesting disable bit 1 = interrupt nesting is disabled 0 = interrupt nesting is enabled bit 14 ovaerr: accumulator a overflow trap flag bit 1 = trap was caused by overflow of accumulator a 0 = trap was not caused by overflow of accumulator a bit 13 ovberr: accumulator b overflow trap flag bit 1 = trap was caused by overflow of accumulator b 0 = trap was not caused by overflow of accumulator b bit 12 covaerr: accumulator a catastrophic overflow trap flag bit 1 = trap was caused by catastrophic overflow of accumulator a 0 = trap was not caused by catastrophic overflow of accumulator a bit 11 covberr: accumulator b catastrophic overflow trap flag bit 1 = trap was caused by catastrophic overflow of accumulator b 0 = trap was not caused by catastrophic overflow of accumulator b bit 10 ovate: accumulator a overflow trap enable bit 1 = trap overflow of accumulator a 0 = trap is disabled bit 9 ovbte: accumulator b overflow trap enable bit 1 = trap overflow of accumulator b 0 = trap is disabled bit 8 covte: catastrophic overflow trap enable bit 1 = trap on catastrophic overflow of accumulator a or b is enabled 0 = trap is disabled bit 7 sftacerr: shift accumulator error status bit 1 = math error trap was caused by an invalid accumulator shift 0 = math error trap was not caused by an invalid accumulator shift bit 6 div0err: arithmetic error status bit 1 = math error trap was caused by a divide-by-zero 0 = math error trap was not caused by a divide-by-zero bit 5 unimplemented: read as ? 0 ? bit 4 matherr: arithmetic error status bit 1 = math error trap has occurred 0 = math error trap has not occurred
? 2011-2014 microchip technology inc. ds70000652f-page 101 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 bit 3 addrerr: address error trap status bit 1 = address error trap has occurred 0 = address error trap has not occurred bit 2 stkerr: stack error trap status bit 1 = stack error trap has occurred 0 = stack error trap has not occurred bit 1 oscfail: oscillator failure trap status bit 1 = oscillator failure trap has occurred 0 = oscillator failure trap has not occurred bit 0 unimplemented: read as ? 0 ? register 7-3: intcon1: interrupt control register 1 (continued)
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 102 ? 2011-2014 microchip technology inc. register 7-4: intcon2: in terrupt control register 2 r/w-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 altivt disi ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? int2ep int1ep int0ep bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 altivt: enable alternate interrupt vector table bit 1 = uses alternate interrupt vector table 0 = uses standard interrupt vector table (default) bit 14 disi: disi instruction status bit 1 = disi instruction is active 0 = disi instruction is not active bit 13-3 unimplemented: read as ? 0 ? bit 2 int2ep: external interrupt 2 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 1 int1ep: external interrupt 1 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 0 int0ep: external interrupt 0 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge
? 2011-2014 microchip technology inc. ds70000652f-page 103 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 7-5: ifs0: interrupt flag status register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ad1if u1txif u1rxif spi1if spi1eif t3if bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 t2if oc2if ic2if ? t1if oc1if ic1if int0if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ad1if: adc1 conversion complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 u1txif: uart1 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 u1rxif: uart1 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 spi1if: spi1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 spi1eif: spi1 fault interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8 t3if: timer3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7 t2if: timer2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 oc2if: output compare channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 ic2if: input capture channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4 unimplemented: read as ? 0 ? bit 3 t1if: timer1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 104 ? 2011-2014 microchip technology inc. bit 2 oc1if: output compare channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 ic1if: input capture channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 int0if: external interrupt 0 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred register 7-5: ifs0: interrupt fla g status register 0 (continued)
? 2011-2014 microchip technology inc. ds70000652f-page 105 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 7-6: ifs1: interrupt flag status register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 ? ?int2ift5if ( 1 ) t4if ( 1 ) ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int1if cnif cmif mi2c1if si2c1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 int2if: external interrupt 2 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 t5if: timer5 interrupt flag status bit ( 1 ) 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 t4if: timer4 interrupt flag status bit ( 1 ) 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10-5 unimplemented: read as ? 0 ? bit 4 int1if: external interrupt 1 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 3 cnif: input change notification interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 cmif: comparator interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 mi2c1if: i2c1 master events interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 si2c1if: i2c1 slave events interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred note 1: these bits are available in dspic33fj32(gp/mc)10x devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 106 ? 2011-2014 microchip technology inc. register 7-7: ifs2: interrupt flag status register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?ic3if ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5 ic3if: input capture channel 3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4-0 unimplemented: read as ? 0 ? register 7-8: ifs3: interrupt flag status register 3 r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 u-0 flta1if ( 1 ) rtcif ? ? ? ?pwm1if ( 1 ) ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 flta1if: pwm1 fault a interrupt flag status bit ( 1 ) 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 14 rtcif: rtcc interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13-10 unimplemented: read as ? 0 ? bit 9 pwm1if: pwm1 interrupt flag status bit ( 1 ) 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8-0 unimplemented: read as ? 0 ? note 1: these bits are available in dspic(16/32)mc10x devices only.
? 2011-2014 microchip technology inc. ds70000652f-page 107 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 7-9: ifs4: interrupt flag status register 4 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?ctmuif ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? u1eif fltb1if ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ctmuif: ctmu interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12-2 unimplemented: read as ? 0 ? bit 1 u1eif: uart1 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 fltb1if: pwm1 fault b interrupt flag status bit ( 1 ) 1 = interrupt request has occurred 0 = interrupt request has not occurred note 1: this bit is available in dspic(16/32)mc102/104 devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 108 ? 2011-2014 microchip technology inc. register 7-10: iec0: interrupt enable control register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ad1ie u1txie u1rxie spi1ie spi1eie t3ie bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 t2ie oc2ie ic2ie ? t1ie oc1ie ic1ie int0ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ad1ie: adc1 conversion complete interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 12 u1txie: uart1 transmitter interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 11 u1rxie: uart1 receiver interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 10 spi1ie: spi1 event interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 9 spi1eie: spi1 error interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 8 t3ie: timer3 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 7 t2ie: timer2 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 6 oc2ie: output compare channel 2 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 5 ic2ie: input capture channel 2 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 4 unimplemented: read as ? 0 ? bit 3 t1ie: timer1 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 2 oc1ie: output compare channel 1 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 1 ic1ie: input capture channel 1 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 int0ie: external interrupt 0 enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled
? 2011-2014 microchip technology inc. ds70000652f-page 109 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 7-11: iec1: interrupt enable control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 ? ? int2ie t5ie ( 1 ) t4ie ( 1 ) ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int1ie cnie cmie mi2c1ie si2c1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 int2ie: external interrupt 2 enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 12 t5ie: timer5 interrupt enable bit ( 1 ) 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 t4ie: timer4 interrupt enable bit ( 1 ) 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10-5 unimplemented: read as ? 0 ? bit 4 int1ie: external interrupt 1 enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 3 cnie: input change notification interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 2 cmie: comparator interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 1 mi2c1ie: i2c1 master events interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 si2c1ie: i2c1 slave events interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled note 1: these bits are available in dspic33fj32(gp/mc)10x devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 110 ? 2011-2014 microchip technology inc. register 7-12: iec2: interrupt enable control register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?ic3ie ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5 ic3ie: input capture channel 3 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 4-0 unimplemented: read as ? 0 ? register 7-13: iec3: interrupt enable control register 3 r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 u-0 flta1ie ( 1 ) rtcie ? ? ? ?pwm1ie ( 1 ) ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 flta1ie: pwm1 fault a interrupt enable bit ( 1 ) 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 14 rtcie: rtcc interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 13-10 unimplemented: read as ? 0 ? bit 9 pwm1ie: pwm1 interrupt enable bit ( 1 ) 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 8-0 unimplemented: read as ? 0 ? note 1: these bits are available in dspic(16/32)mc10x devices only.
? 2011-2014 microchip technology inc. ds70000652f-page 111 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 7-14: iec4: interrupt enable control register 4 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?ctmuie ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? u1eie fltb1ie ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ctmuie: ctmu interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 12-2 unimplemented: read as ? 0 ? bit 1 u1eie: uart1 error interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 fltb1ie: pwm1 fault b interrupt enable bit ( 1 ) 1 = interrupt request has occurred 0 = interrupt request has not occurred note 1: this bit is available in dspic(16/32)mc102/104 devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 112 ? 2011-2014 microchip technology inc. register 7-15: ipc0: interrupt pr iority control register 0 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? t1ip2 t1ip1 t1ip0 ? oc1ip2 oc1ip1 oc1ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ic1ip2 ic1ip1 ic1ip0 ? int0ip2 int0ip1 int0ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t1ip<2:0>: timer1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc1ip<2:0>: output compare channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic1ip<2:0>: input capture channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 int0ip<2:0>: external interrupt 0 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2011-2014 microchip technology inc. ds70000652f-page 113 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 7-16: ipc1: interrupt pr iority control register 1 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? t2ip2 t2ip1 t2ip0 ? oc2ip2 oc2ip1 oc2ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ic2ip2 ic2ip1 ic2ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t2ip<2:0>: timer2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc2ip<2:0>: output compare channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic2ip<2:0>: input capture channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 114 ? 2011-2014 microchip technology inc. register 7-17: ipc2: interrupt pr iority control register 2 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? u1rxip2 u1rxip1 u1rxip0 ? spi1ip2 spi1ip1 spi1ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? spi1eip2 spi1eip1 spi1eip0 ?t3ip2t3ip1t3ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 u1rxip<2:0>: uart1 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 spi1ip<2:0>: spi1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 spi1eip<2:0>: spi1 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 t3ip<2:0>: timer3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2011-2014 microchip technology inc. ds70000652f-page 115 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 7-18: ipc3: interrupt pr iority control register 3 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ad1ip2 ad1ip1 ad1ip0 ? u1txip2 u1txip1 u1txip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 ad1ip<2:0>: adc1 conversion complete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 u1txip<2:0>: uart1 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 116 ? 2011-2014 microchip technology inc. register 7-19: ipc4: interrupt pr iority control register 4 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? cnip2 cnip1 cnip0 ? cmip2 cmip1 cmip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? mi2c1ip2 mi2c1ip1 mi2c1ip0 ? si2c1ip2 si2c1ip1 si2c1ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 cnip<2:0>: change notification interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 cmip<2:0>: comparator interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 mi2c1ip<2:0>: i2c1 master events interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 si2c1ip<2:0>: i2c1 slave events interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2011-2014 microchip technology inc. ds70000652f-page 117 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 7-20: ipc5: interrupt pr iority control register 5 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? int1ip2 int1ip1 int1ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 2-0 int1ip<2:0>: external interrupt 1 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled register 7-21: ipc6: interrupt pr iority control register 6 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ?t4ip2 ( 1 ) t4ip1 ( 1 ) t4ip0 ( 1 ) ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t4ip<2:0>: timer4 interrupt priority bits ( 1 ) 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11-0 unimplemented: read as ? 0 ? note 1: these bits are available in dspic33fj32(gp/mc)10x devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 118 ? 2011-2014 microchip technology inc. register 7-22: ipc7: interrupt pr iority control register 7 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? int2ip2 int2ip1 int2ip0 ?t5ip2 ( 1 ) t5ip1 ( 1 ) t5ip0 ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 int2ip<2:0>: external interrupt 2 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 t5ip<2:0>: timer5 interrupt priority bits ( 1 ) 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled note 1: these bits are available in dspic33fj32(gp/mc)10x devices only.
? 2011-2014 microchip technology inc. ds70000652f-page 119 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 7-23: ipc9: interrupt pr iority control register 9 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ic3ip2 ic3ip1 ic3ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 ic3ip<2:0>: external interrupt 3 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ? register 7-24: ipc14: interrupt priority control register 14 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ?pwm1ip2 ( 1 ) pwm1ip1 ( 1 ) pwm1ip0 ( 1 ) ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 pwm1ip<2:0>: pwm1 interrupt priority bits ( 1 ) 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ? note 1: these bits are available in dspic(16/32)mc10x devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 120 ? 2011-2014 microchip technology inc. register 7-25: ipc15: interrupt priority control register 15 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ?flta1ip2 ( 1 ) flta1ip1 ( 1 ) flta1ip0 ( 1 ) ? rtcip2 rtcip1 rtcip0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 flta1ip<2:0>: pwm1 fault a interrupt priority bits ( 1 ) 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 rtcip<2:0>: rtcc interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7-0 unimplemented: read as ? 0 ? note 1: these bits are available in dspic(16/32)mc10x devices only.
? 2011-2014 microchip technology inc. ds70000652f-page 121 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 7-26: ipc16: interrupt priority control register 16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 ? u1eip2 u1eip1 u1eip0 ?fltb1ip2 ( 1 ) fltb1ip1 ( 1 ) fltb1ip0 ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 u1eip<2:0>: uart1 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 fltb1ip<2:0>: pwm1 fault b interrupt priority bits ( 1 ) 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled note 1: these bits are available in dspic(16/32)mc102/104 devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 122 ? 2011-2014 microchip technology inc. register 7-27: ipc19: interrupt priority control register 19 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ctmuip2 ctmuip1 ctmuip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 ctmuip<2:0>: ctmu interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
? 2011-2014 microchip technology inc. ds70000652f-page 123 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 7-28: inttreg: interrupt control and status register u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 ? ? ? ? ilr3 ilr2 ilr1 ilr0 bit 15 bit 8 u-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as ? 0 ? bit 11-8 ilr<3:0>: new cpu interrupt priority level bits 1111 = cpu interrupt priority level is 15 ? ? ? 0001 = cpu interrupt priority level is 1 0000 = cpu interrupt priority level is 0 bit 7 unimplemented: read as ? 0 ? bit 6-0 vecnum<6:0>: vector number of pending interrupt bits 0111111 = interrupt vector pending is number 135 ? ? ? 0000001 = interrupt vector pending is number 9 0000000 = interrupt vector pending is number 8
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 124 ? 2011-2014 microchip technology inc. 7.4 interrupt setup procedures 7.4.1 initialization to configure an interrupt source at initialization: 1. set the nstdis bit (intcon1<15>) if nested interrupts are not desired. 2. select the user-assigned priority level for the interrupt source by writing the control bits into the appropriate ipcx register. the priority level will depend on the specific application and type of interrupt source. if multiple priority levels are not desired, the ipcx register control bits for all enabled interrupt sources can be programmed to the same non-zero value. 3. clear the interrupt flag status bit associated with the peripheral in the associated ifsx register. 4. enable the interrupt source by setting the inter- rupt enable control bit associated with the source in the appropriate iecx register. 7.4.2 interrupt service routine the method used to declare an isr and initialize the ivt with the correct vector address depends on the programming language (c or assembler), and the language development toolsuite used to develop the application. in general, the user application must clear the interrupt flag in the appropriate ifsx register for the source of interrupt that the isr handles. otherwise, the program will re-enter the isr immediately after exiting the routine. if the isr is coded in assembly language, it must be terminated using a retfie instruction to unstack the saved pc value, srl value and old cpu priority level. 7.4.3 trap service routine a trap service routine (tsr) is coded like an isr, except that the appropriate trap status flag in the intcon1 register must be cleared to avoid re-entry into the tsr. 7.4.4 interrupt disable all user interrupts can be disabled using this procedure: 1. push the current sr value onto the software stack using the push instruction. 2. force the cpu to priority level 7 by inclusive oring the value oeh with srl. to enable user interrupts, the pop instruction can be used to restore the previous sr value. the disi instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. level 7 interrupt sources are not disabled by the disi instruction. note: at a device reset, the ipcx registers are initialized such that all user interrupt sources are assigned to interrupt priority level 4. note: only user interrupts with a priority level of 7 or lower can be disabled. trap sources (level 8-level 15) cannot be disabled.
? 2011-2014 microchip technology inc. ds70000652f-page 125 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 8.0 oscillator configuration the oscillator system for dspic33fj16(gp/mc)101/ 102 and dspic33fj32(gp/mc)101/102/104 devices provides: ? external and internal oscillator options as clock sources ? an on-chip, 4x phase lock loop (pll) to scale the internal operating frequency to the required system clock frequency ? an internal frc oscillator that can also be used with the pll, thereby allowing full-speed operation without any external clock generation hardware ? clock switching between various clock sources ? programmable clock postscaler for system power savings ? a fail-safe clock monitor (fscm) that detects clock failure and takes fail-safe measures ? an oscillator control register (osccon) ? nonvolatile configuration bits for main oscillator selection a simplified diagram of the oscillator system is shown in figure 8-1 . figure 8-1: oscillator system diagram note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to com- plement the information in this data sheet, refer to ?oscillator (part vi)? (ds70644) in the ?dspic33/pic24 family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. note 1: if the oscillator is used with ms or hs modes, an extended parallel resistor with the value of 1 m ? must be connected. 2: the term, f p , refers to the clock source for all peripherals, while f cy refers to the clock source for the cpu. throughout this docu- ment, f cy and f p are used interchangeably, except in the case of doze mode. f p and f cy will be different when doze mode is used with a doze ratio of 1:2 or lower. secondary oscillator (sosc) lposcen sosco sosci timer 1 mspll, ecpll, ms, hs, ec frcdiv<2:0> wdt, pwrt, fscm frcdivn sosc frcdiv16 frcpll nosc<2:0> fnosc<2:0> reset frc oscillator lprc oscillator doze<2:0> s3 s1 s2 s1/s3 s7 s6 frc lprc s0 s5 s4 clock switch s7 clock fail 2 tun<5:0> 4x pll f cy (2) frcdiv doze osc2 osc1 primary oscillator (posc) r (1) poscmd<1:0> f p (2) f osc (to peripherals) 16
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 126 ? 2011-2014 microchip technology inc. 8.1 cpu clocking system the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices provide seven system clock options: ? fast rc (frc) oscillator ? frc oscillator with 4x pll ? primary (ms, hs or ec) oscillator ? primary oscillator with 4x pll ? secondary (lp) oscillator ? low-power rc (lprc) oscillator ? frc oscillator with postscaler 8.1.1 system clock sources 8.1.1.1 fast rc the fast rc (frc) internal oscillator runs at a nominal frequency of 7.37 mhz. user software can tune the frc frequency. user software can optionally specify a factor (ranging from 1:2 to 1:256) by which the frc clock frequency is divided. this factor is selected using the frcdiv<2:0> (clkdiv<10:8>) bits. the frc frequency depends on the frc accuracy (see table 26-18 ) and the value of the frc oscillator tuning register (see register 8-3 ). 8.1.1.2 primary the primary oscillator can use one of the following as its clock source: ? ms (crystal): crystals and ceramic resonators in the range of 4 mhz to 10 mhz. the crystal is connected to the osc1 and osc2 pins. ? hs (high-speed crystal): crystals in the range of 10 mhz to 32 mhz. the crystal is connected to the osc1 and osc2 pins. ? ec (external clock): the external clock signal is directly applied to the osc1 pin. 8.1.1.3 secondary the secondary (lp) oscillator is designed for low power and uses a 32.768 khz crystal or ceramic resonator. the lp oscillator uses the sosci and sosco pins. 8.1.1.4 low-power rc the low-power rc (lprc) internal oscillator runs at a nominal frequency of 32.768 khz. it is also used as a reference clock by the watchdog timer (wdt) and fail-safe clock monitor (fscm). 8.1.1.5 pll the clock signals generated by the frc and primary oscillators can be optionally applied to an on-chip, 4x phase lock loop (pll) to provide faster output frequencies for device operation. pll configuration is described in section 8.1.3 ?pll configuration? . 8.1.2 system clock selection the oscillator source used at a device power-on reset event is selected using configuration bit settings. the oscillator configuration bit settings are located in the configuration registers in the program memory. (refer to section 23.1 ?configuration bits? for further details.) the initial oscillator selection configuration bits, fnosc<2:0> (foscsel<2:0>), and the primary oscillator mode select configuration bits, poscmd<1:0> (fosc<1:0>), select the oscillator source that is used at a power-on reset. the frc primary oscillator is the default (unprogrammed) selection. the configuration bits allow users to choose among 12 different clock modes, shown in tab l e 8 - 1 . the output of the oscillator (or the output of the pll if a pll mode has been selected) f osc is divided by 2 to generate the device instruction clock (f cy ) and the peripheral clock time base (f p ). f cy defines the operating speed of the device, and speeds up to 16 mhz are supported by the dspic33fj16(gp/ mc)101/102 and dspic33fj32(gp/mc)101/102/104 architecture. instruction execution speed or device operating frequency, f cy , is given by: equation 8-1: device operating frequency f cy f osc 2 ------------- =
? 2011-2014 microchip technology inc. ds70000652f-page 127 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 8.1.3 pll configuration the primary oscillator and internal frc oscillator can optionally use an on-chip, 4x pll to obtain higher speeds of operation. for example, suppose an 8 mhz crystal is being used with the selected oscillator mode of ms with pll. this provides a f osc of 8 mhz * 4 = 32 mhz. the resultant device operating speed is 32/2 = 16 mips. equation 8-2: ms with pll mode example table 8-1: configuration bit va lues for clock selection f cy = = 1 2 f osc 2 (8000000 ? 4) = 16 mips oscillator mode oscillator source poscmd<1:0> fnosc<2:0> see note fast rc oscillator with divide-by-n (frcdivn) internal xx 111 1 , 2 fast rc oscillator with divide-by-16 (frcdiv16) internal xx 110 1 low-power rc oscillator (lprc) internal xx 101 1 secondary (timer1) oscillator (sosc) secondary xx 100 1 primary oscillator (ms) with pll (mspll) primary 01 011 primary oscillator (ec) with pll (ecpll) primary 00 011 1 primary oscillator (hs) primary 10 010 primary oscillator (ms) primary 01 010 primary oscillator (ec) primary 00 010 1 fast rc oscillator (frc) with divide-by-n and pll (frcpll) internal xx 001 1 fast rc oscillator (frc) internal xx 000 1 note 1: osc2 pin function is determined by the osciofnc configuration bit. 2: this is the default oscillator mode for an unprogrammed (erased) device.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 128 ? 2011-2014 microchip technology inc. 8.2 oscillator control registers register 8-1: osccon: os cillator control register ( 1 ) u-0 r-0 r-0 r-0 u-0 r/w-y r/w-y r/w-y ? cosc2 cosc1 cosc0 ?nosc2 ( 2 ) nosc1 ( 2 ) nosc0 ( 2 ) bit 15 bit 8 r/w-0 r/w-0 r-0 u-0 r/c-0 u-0 r/w-0 r/w-0 clklock iolock lock ?cf ? lposcen oswen bit 7 bit 0 legend: c = clearable bit y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 cosc<2:0>: current oscillator selection bits (read-only) 111 = fast rc oscillator (frc) with divide-by-n 110 = fast rc oscillator (frc) with divide-by-16 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator (ms, ec) with pll 010 = primary oscillator (ms, hs, ec) 001 = fast rc oscillator (frc) with divide-by-n and pll (frcpll) 000 = fast rc oscillator (frc) bit 11 unimplemented: read as ? 0 ? bit 10-8 nosc<2:0>: new oscillator selection bits ( 2 ) 111 = fast rc oscillator (frc) with divide-by-n 110 = fast rc oscillator (frc) with divide-by-16 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator (ms, ec) with pll 010 = primary oscillator (ms, hs, ec) 001 = fast rc oscillator (frc) with divide-by-n and pll (frcpll) 000 = fast rc oscillator (frc) bit 7 clklock: clock lock enable bit if clock switching is enabled and fscm is disabled (fcksm<1:0> (fosc<7:6>) = 0b01 ): 1 = clock switching is disabled, system clock source is locked 0 = clock switching is enabled, system clock source can be modified by clock switching bit 6 iolock: peripheral pin select lock bit 1 = peripheral pin select is locked, a write to peripheral pin select registers is not allowed 0 = peripheral pin select is not locked, a write to peripheral pin select registers is allowed bit 5 lock: pll lock status bit (read-only) 1 = indicates that pll is in lock or pll start-up timer is satisfied 0 = indicates that pll is out of lock, start-up timer is in progress or pll is disabled bit 4 unimplemented: read as ? 0 ? note 1: writes to this register require an unlock sequence. refer to ?oscillator (part vi)? (ds70644) in the ?dspic33/pic24 family reference manual? for details. 2: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direction. in these instances, the application must switch to frc mode as a transitional clock source between the two pll modes.
? 2011-2014 microchip technology inc. ds70000652f-page 129 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 bit 3 cf: clock fail detect bit (read/clear by application) 1 = fscm has detected a clock failure 0 = fscm has not detected a clock failure bit 2 unimplemented: read as ? 0 ? bit 1 lposcen: secondary (lp) oscillator enable bit 1 = enables secondary oscillator 0 = disables secondary oscillator bit 0 oswen: oscillator switch enable bit 1 = requests oscillator switch to selection specified by the nosc<2:0> bits 0 = oscillator switch is complete register 8-1: osccon: os cillator control register ( 1 ) (continued) note 1: writes to this register require an unlock sequence. refer to ?oscillator (part vi)? (ds70644) in the ?dspic33/pic24 family reference manual? for details. 2: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direction. in these instances, the application must switch to frc mode as a transitional clock source between the two pll modes.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 130 ? 2011-2014 microchip technology inc. register 8-2: clkdiv: clock divisor register r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 roi doze2 ( 2 , 3 ) doze1 ( 2 , 3 ) doze0 ( 2 , 3 ) dozen ( 1 , 2 , 3 ) frcdiv2 frcdiv1 frcdiv0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 roi: recover on interrupt bit 1 = interrupts will clear the dozen bit and the processor clock/peripheral clock ratio is set to 1:1 0 = interrupts have no effect on the dozen bit bit 14-12 doze<2:0>: processor clock reduction select bits ( 2 , 3 ) 111 = f cy /128 110 = f cy /64 101 = f cy /32 100 = f cy /16 011 = f cy /8 (default) 010 = f cy /4 001 = f cy /2 000 = f cy /1 bit 11 dozen: doze mode enable bit ( 1 , 2 , 3 ) 1 = doze<2:0> bits field specifies the ratio between the peripheral clocks and the processor clocks 0 = processor clock/peripheral clock ratio is forced to 1:1 bit 10-8 frcdiv<2:0>: internal fast rc oscillator postscaler bits 111 = frc divide-by-256 110 = frc divide-by-64 101 = frc divide-by-32 100 = frc divide-by-16 011 = frc divide-by-8 010 = frc divide-by-4 001 = frc divide-by-2 000 = frc divide-by-1 (default) bit 7-0 unimplemented: read as ? 0 ? note 1: this bit is cleared when the roi bit is set and an interrupt occurs. 2: if dozen = 1 , writes to doze<2:0> are ignored. 3: if doze<2:0> = 000 , the dozen bit cannot be set by the user; writes are ignored.
? 2011-2014 microchip technology inc. ds70000652f-page 131 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 8-3: osctun: frc oscillator tuning register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frc oscillator tuning bits 011111 = maximum frequency deviation of 1.453% (7.477 mhz) 011110 = center frequency + 1.406% (7.474 mhz) ? ? ? 000001 = center frequency + 0.047% (7.373 mhz) 000000 = center frequency (7.37 mhz nominal) 111111 = center frequency ? 0.047% (7.367 mhz) ? ? ? 100001 = center frequency ? 1.453% (7.263 mhz) 100000 = minimum frequency deviation of -1.5% (7.259 mhz)
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 132 ? 2011-2014 microchip technology inc. 8.3 clock switching operation applications are free to switch among any of the four clock sources (primary, lp, frc and lprc) under software control at any time. to limit the possible side effects of this flexibility, dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices have a safeguard lock built into the switch process. 8.3.1 enabling clock switching to enable clock switching, the fcksm1 configuration bit in the fosc configuration register must be programmed to ? 0 ?. (refer to section 23.1 ?configuration bits? for further details.) if the fcksm1 configuration bit is unpro- grammed (? 1 ?), the clock switching function and fail-safe clock monitor function are disabled. this is the default setting. the noscx control bits (osccon<10:8>) do not control the clock selection when clock switching is disabled. how- ever, the coscx bits (osccon<14:12>) reflect the clock source selected by the fnoscx configuration bits. the oswen control bit (osccon<0>) has no effect when clock switching is disabled; it is held at ? 0 ? at all times. 8.3.2 oscillator switching sequence performing a clock switch requires this basic sequence: 1. if desired, read the cosc bits (osccon<14:12>) to determine the current oscillator source. 2. perform the unlock sequence to allow a write to the osccon register high byte. 3. write the appropriate value to the noscx con- trol bits (osccon<10:8>) for the new oscillator source. 4. perform the unlock sequence to allow a write to the osccon register low byte. 5. set the oswen bit (osccon<0>) to initiate the oscillator switch. once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. the clock switching hardware compares the coscx status bits with the new value of the noscx control bits. if they are the same, the clock switch is a redundant operation. in this case, the oswen bit is cleared automatically and the clock switch is aborted. 2. if a valid clock switch has been initiated, the lock and cf (osccon<5,3>) status bits are cleared. 3. the new oscillator is turned on by the hardware if it is not currently running. if a crystal oscillator must be turned on, the hardware waits until the oscillator start-up timer (ost) expires. if the new source is using the pll, the hardware waits until a pll lock is detected (lock = 1 ). 4. the hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. 5. the hardware clears the oswen bit to indicate a successful clock transition. in addition, the noscx bit values are transferred to the coscx status bits. 6. the old clock source is turned off at this time, with the exception of lprc (if wdt or fscm is enabled) or lp (if lposcen remains set). 8.4 fail-safe clock monitor (fscm) the fail-safe clock monitor (fscm) allows the device to continue to operate even in the event of an oscillator failure. the fscm function is enabled by programming. if the fscm function is enabled, the lprc internal oscillator runs at all times (except during sleep mode) and is not subject to control by the watchdog timer. in the event of an oscillator failure, the fscm generates a clock failure trap event and switches the system clock over to the frc oscillator. then, the application program can either attempt to restart the oscillator or execute a controlled shutdown. the trap can be treated as a warm reset by simply loading the reset address into the oscillator fail trap vector. if the pll multiplier is used to scale the system clock, the internal frc is also multiplied by the same factor on clock failure. essentially, the device switches to frc with pll on a clock failure. note: primary oscillator mode has three different submodes (ms, hs and ec), which are determined by the poscmd<1:0> config- uration bits. while an application can switch to and from primary oscillator mode in software, it cannot switch among the different primary submodes without reprogramming the device. note 1: the processor continues to execute code throughout the clock switching sequence. timing-sensitive code should not be executed during this time. 2: direct clock switches between any pri- mary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direc- tion. in these instances, the application must switch to frc mode as a transition clock source between the two pll modes. 3: refer to ?oscillator (part vi)? (ds70644) in the ?dspic33/pic24 family reference manual? for details.
? 2011-2014 microchip technology inc. ds70000652f-page 133 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 9.0 power-saving features the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices provide the ability to manage power consumption by selectively managing clocking to the cpu and the peripherals. in general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. devices can manage power consumption in four different ways: ? clock frequency ? instruction-based sleep and idle modes ? software-controlled doze mode ? selective peripheral control in software combinations of these methods can be used to selec- tively tailor an application?s power consumption while still maintaining critical application features, such as timing-sensitive communications. 9.1 clock frequency and clock switching dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/ mc)101/102/104 devices allow a wide range of clock frequencies to be selected under application control. if the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the nosc<2:0> bits (osccon<10:8>). the process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in section 8.0 ?oscillator configuration? . 9.2 instruction-based power-saving modes dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/ mc)101/102/104 devices have two special power- saving modes that are entered through the execution of a special pwrsav instruction. sleep mode stops clock operation and halts all code execution. idle mode halts the cpu and code execution, but allows peripheral modules to continue operation. the assembler syntax of the pwrsav instruction is shown in example 9-1 . sleep and idle modes can be exited as a result of an enabled interrupt, wdt time-out or a device reset. when the device exits these modes, it is said to wake-up. 9.2.1 sleep mode the following occurs in sleep mode: ? the system clock source is shut down. if an on-chip oscillator is used, it is turned off. ? the device current consumption is reduced to a minimum, provided that no i/o pin is sourcing current ? the fail-safe clock monitor does not operate, since the system clock source is disabled ? the lprc clock continues to run in sleep mode if the wdt is enabled ? the wdt, if enabled, is automatically cleared prior to entering sleep mode ? some device features or peripherals may continue to operate. this includes items such as the input change notification (icn) on the i/o ports or peripherals that use an external clock input. ? any peripheral that requires the system clock source for its operation is disabled the device will wake-up from sleep mode on any of the these events: ? any interrupt source that is individually enabled ? any form of device reset ? a wdt time-out on wake-up from sleep mode, the processor restarts with the same clock source that was active when sleep mode was entered. example 9-1: pwrsav instruction syntax note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to ?watchdog timer and power-saving modes? (ds70196) in the ?dspic33/pic24 family reference man- ual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. note: sleep_mode and idle_mode are constants defined in the assembler include file for the selected device. pwrsav #sleep_mode ; put the device into sleep mode pwrsav #idle_mode ; put the device into idle mode
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 134 ? 2011-2014 microchip technology inc. 9.2.2 idle mode the following occurs in idle mode: ? the cpu stops executing instructions. ? the wdt is automatically cleared. ? the system clock source remains active. by default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see section 9.4 ?peripheral module disable? ). ? if the wdt or fscm is enabled, the lprc also remains active. the device will wake from idle mode on any of these events: ? any interrupt that is individually enabled ? any device reset ? a wdt time-out on wake-up from idle mode, the clock is reapplied to the cpu and instruction execution will begin (2-4 clock cycles later), starting with the instruction following the pwrsav instruction, or the first instruction in the isr. 9.2.3 interrupts coincident with power save instructions any interrupt that coincides with the execution of a pwrsav instruction is held off until entry into sleep or idle mode has completed. the device then wakes up from sleep or idle mode. 9.3 doze mode the preferred strategies for reducing power consumption are changing clock speed and invoking one of the power- saving modes. in some circumstances, this may not be practical. for example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. reducing system clock speed can introduce communication errors, while using a power-saving mode can stop communications completely. doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. in this mode, the system clock continues to operate from the same source and at the same speed. peripheral modules continue to be clocked at the same speed, while the cpu clock speed is reduced. synchronization between the two clock domains is maintained, allowing the peripherals to access the sfrs while the cpu executes code at a slower rate. doze mode is enabled by setting the dozen bit (clkdiv<11>). the ratio between peripheral and core clock speed is determined by the doze<2:0> bits (clkdiv<14:12>). there are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default setting. programs can use doze mode to selectively reduce power consumption in event-driven applications. this allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the cpu idles, waiting for something to invoke an interrupt routine. an automatic return to full-speed cpu operation on interrupts can be enabled by setting the roi bit (clkdiv<15>). by default, interrupt events have no effect on doze mode operation. for example, suppose the device is operating at 20 mips and the uart module has been configured for 500 kbps based on this device operating speed. if the device is placed in doze mode with a clock frequency ratio of 1:4, the uart module continues to communicate at the required bit rate of 500 kbps, but the cpu now starts executing instructions at a frequency of 5 mips. 9.4 peripheral module disable the peripheral module disable (pmdx) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. when a peripheral is disabled using the appropriate pmdx control bit, the peripheral is in a minimum power consumption state. the control and status registers associated with the peripheral are also disabled, so writes to those registers will have no effect and read values will be invalid. a peripheral module is enabled only if both the associated bit in the pmdx register is cleared and the peripheral is supported by the specific dspic ? dsc variant. if the peripheral is present in the device, it is enabled in the pmdx register by default. note: if a pmdx bit is set, the corresponding module is disabled after a delay of one instruction cycle. similarly, if a pmdx bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable module operation).
? 2011-2014 microchip technology inc. ds70000652f-page 135 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 9.5 pmd control registers register 9-1: pmd1: peripheral mo dule disable control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 t5md ( 1 ) t4md ( 1 ) t3md t2md t1md ?pwm1md ? bit 15 bit 8 r/w-0 u-0 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 i2c1md ?u1md ? spi1md ? ?ad1md ( 2 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 t5md: timer5 module disable bit ( 1 ) 1 = timer5 module is disabled 0 = timer5 module is enabled bit 14 t4md: timer4 module disable bit ( 1 ) 1 = timer4 module is disabled 0 = timer4 module is enabled bit 13 t3md: timer3 module disable bit 1 = timer3 module is disabled 0 = timer3 module is enabled bit 12 t2md: timer2 module disable bit 1 = timer2 module is disabled 0 = timer2 module is enabled bit 11 t1md: timer1 module disable bit 1 = timer1 module is disabled 0 = timer1 module is enabled bit 10 unimplemented: read as ? 0 ? bit 9 pwm1md: pwm1 module disable bit 1 = pwm1 module is disabled 0 = pwm1 module is enabled bit 8 unimplemented: read as ? 0 ? bit 7 i2c1md: i2c1 module disable bit 1 = i2c1 module is disabled 0 = i2c1 module is enabled bit 6 unimplemented: read as ? 0 ? bit 5 u1md: uart1 module disable bit 1 = uart1 module is disabled 0 = uart1 module is enabled bit 4 unimplemented: read as ? 0 ? note 1: these bits are available in dspic33fj32(gp/mc)10x devices only. 2: pcfgx bits have no effect if the adc module is disabled by setting this bit. when the bit is set, all port pins that have been multiplexed with anx will be in digital mode.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 136 ? 2011-2014 microchip technology inc. register 9-2: pmd2: peripheral mo dule disable control register 2 bit 3 spi1md: spi1 module disable bit 1 = spi1 module is disabled 0 = spi1 module is enabled bit 2-1 unimplemented: read as ? 0 ? bit 0 ad1md: adc1 module disable bit ( 2 ) 1 = adc1 module is disabled 0 = adc1 module is enabled u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? ic3md ic2md ic1md bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ?oc2mdoc1md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10 ic3md: input capture 3 module disable bit 1 = input capture 3 module is disabled 0 = input capture 3 module is enabled bit 9 ic2md: input capture 2 module disable bit 1 = input capture 2 module is disabled 0 = input capture 2 module is enabled bit 8 ic1md: input capture 1 module disable bit 1 = input capture 1 module is disabled 0 = input capture 1 module is enabled bit 7-2 unimplemented: read as ? 0 ? bit 1 oc2md: output compare 2 module disable bit 1 = output compare 2 module is disabled 0 = output compare 2 module is enabled bit 0 oc1md: output compare 1 module disable bit 1 = output compare 1 module is disabled 0 = output compare 1 module is enabled register 9-1: pmd1: peripheral module disable control register 1 (continued) note 1: these bits are available in dspic33fj32(gp/mc)10x devices only. 2: pcfgx bits have no effect if the adc module is disabled by setting this bit. when the bit is set, all port pins that have been multiplexed with anx will be in digital mode.
? 2011-2014 microchip technology inc. ds70000652f-page 137 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 9-3: pmd3: peripheral mo dule disable control register 3 register 9-4: pmd4: peripheral mo dule disable control register 4 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 ? ? ? ? ? cmpmd rtccmd ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10 cmpmd: comparator module disable bit 1 = comparator module is disabled 0 = comparator module is enabled bit 9 rtccmd: rtcc module disable bit 1 = rtcc module is disabled 0 = rtcc module is enabled bit 8-0 unimplemented: read as ? 0 ? u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 u-0 ? ? ? ? ?ctmumd ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 2 ctmumd: ctmu module disable bit 1 = ctmu module is disabled 0 = ctmu module is enabled bit 1-0 unimplemented: read as ? 0 ?
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 138 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 139 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 10.0 i/o ports all of the device pins (except v dd , v ss , mclr and osc1/clki) are shared among the peripherals and the parallel i/o ports. all i/o input ports feature schmitt trigger inputs for improved noise immunity. 10.1 parallel i/o (pio) ports generally a parallel i/o port that shares a pin with a peripheral is subservient to the peripheral. the peripheral?s output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the i/o pin. the logic also prevents ?loop through,? in which a port?s digital output can drive the input of a peripheral that shares the same pin. figure 10-1 shows how ports are shared with other peripherals and the associated i/o pin to which they are connected. when a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. the i/o pin can be read, but the output driver for the parallel port bit is disabled. if a peripheral is enabled, but the peripheral is not actively driving a pin, that pin can be driven by a port. all port pins have three registers directly associated with their operation as digital i/o. the data direction register (trisx) determines whether the pin is an input or an output. if the data direction bit is a ? 1 ?, the pin is an input. all port pins are defined as inputs after a reset. reads from the output latch (latx) register read the latch. writes to the output latch register write the latch. reads from the port (portx) read the port pins, while writes to the port pins write the latch. any bit and its associated data and control registers that is not valid for a particular device will be disabled. this means the corresponding latx and trisx registers and the port pin will read as zeros. when a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to com- plement the information in this data sheet, refer to ?i/o ports? (ds70193) in the ?dspic33/pic24 family reference man- ual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 140 ? 2011-2014 microchip technology inc. figure 10-1: block diag ram of a typical shared port structure q d ck wr lat + tris latch i/o pin wr port data bus q d ck data latch read port read tris 1 0 1 0 wr tris peripheral output data output enable peripheral input data i/o peripheral module peripheral output enable pio module output multiplexers output data input data peripheral module enable read lat
? 2011-2014 microchip technology inc. ds70000652f-page 141 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 10.1.1 open-drain configuration in addition to the portx, latx and trisx registers for data control, some port pins can also be individually configured for either digital or open-drain output. this is controlled by the open-drain control register, odcx, associated with each port. setting any of the bits configures the corresponding pin to act as an open-drain output. the open-drain feature allows the generation of outputs higher than v dd (e.g., 5v) on any desired 5v tolerant pins by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification. see ? pin diagrams ? for the available pins and their functionality. 10.2 configuring analog port pins the ad1pcfgl and trisx registers control the oper- ation of the analog-to-digital port pins. the port pins that are to function as analog inputs must have their corresponding trisx bit set (input). if the trisx bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the ad1pcfgl register has a default value of 0x0000; therefore, all pins that share anx functions are analog (not digital) by default. when the portx register is read, all pins configured as analog input channels will read as cleared (a low level). pins configured as digital inputs will not convert an analog input. analog levels on any pin defined as a digital input (including the anx pins) can cause the input buffer to consume current that exceeds the device specifications. 10.2.1 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically this instruction would be a nop . a demonstration is shown in example 10-1 . 10.3 input change notification (icn) the input change notification function of the i/o ports allows the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices to gener- ate interrupt requests to the processor in response to a change-of-state (cos) on selected input pins. this feature can detect input change-of-states, even in sleep mode, when the clocks are disabled. depending on the device pin count, up to 21 external signals (cnx pin) can be selected (enabled) for generating an interrupt request on a change-of-state. four control registers are associated with the cn module. the cnen1 and cnen2 registers contain the interrupt enable control bits for each of the cn input pins. setting any of these bits enables a cn interrupt for the corresponding pins. each cn pin also has a weak pull-up connected to it. the pull-ups act as a current source connected to the pin and eliminate the need for external resistors when push button or keypad devices are connected. the pull-ups are enabled separately using the cnpu1 and cnpu2 registers, which contain the control bits for each of the cn pins. setting any of the control bits enables the weak pull-ups for the corresponding pins. example 10-1: port write/read example note: pull-ups on input change notification pins should always be disabled when the port pin is configured as a digital output. mov 0xff00, w0 ; configure portb<15:8> as inputs mov w0, trisbb ; and portb<7:0> as outputs nop ; delay 1 cycle btss portb, #13 ; next instruction
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 142 ? 2011-2014 microchip technology inc. 10.4 peripheral pin select (pps) peripheral pin select configuration enables peripheral set selection and placement on a wide range of i/o pins. by increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. the peripheral pin select configuration feature operates over a fixed subset of digital i/o pins. pro- grammers can independently map the input and/or output of most digital peripherals to any one of these i/o pins. peripheral pin select is performed in soft- ware and generally does not require the device to be reprogrammed. hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping, once it has been established. 10.4.1 available pins the peripheral pin select feature is used with a range of up to 16 pins. the number of available pins depends on the particular device and its pin count. pins that support the peripheral pin select feature include the designation ?rpn? in their full pin designation, where ?rp? designates a remappable peripheral and ?n? is the remappable pin number. 10.4.2 controlling peripheral pin select peripheral pin select features are controlled through two sets of special function registers: one to map peripheral inputs and one to map outputs. because they are separately controlled, a particular peripheral?s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. the association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. 10.4.2.1 input mapping the inputs of the peripheral pin select options are mapped on the basis of the peripheral. a control register associated with a peripheral dictates the pin it will be mapped to. the rpinrx registers are used to configure peripheral input mapping (see register 10-1 through register 10-10 ). each register contains sets of 5-bit fields, with each set associated with one of the remappable peripherals. programming a given peripheral?s bit field with an appropriate 5-bit value maps the rpn pin with that value to that peripheral. for any given device, the valid range of values for any bit field corresponds to the maximum number of peripheral pin selections supported by the device. figure 10-2 illustrates remappable pin selection for u1rx input. figure 10-2: remappable mux input for u1rx note: for input mapping only, the peripheral pin select (pps) functionality does not have priority over the trisx settings. there- fore, when configuring the rpx pin for input, the corresponding bit in the trisx register must also be configured for input (i.e., set to ? 1 ?). rp0 rp1 rp2 rp 25 0 25 1 2 u1rx input u1rxr<4:0> to peripheral
? 2011-2014 microchip technology inc. ds70000652f-page 143 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 10-1: selectable input so urces (maps input to function) ( 1 ) input name function name register configuration bits external interrupt 1 int1 rpinr0 int1r<4:0> external interrupt 2 int2 rpinr1 int2r<4:0> timer2 external clock t2ck rpinr3 t2ckr<4:0> timer3 external clock t3ck rpinr3 t3ckr<4:0> timer4 external clock t4ck rpinr4 t4ckr<4:0> ( 2 ) timer5 external clock t5ck rpinr4 t5ckr<4:0> ( 2 ) input capture 1 ic1 rpinr7 ic1r<4:0> input capture 2 ic2 rpinr7 ic2r<4:0> input capture 3 ic3 rpinr8 ic3r<4:0> output compare fault a ocfa rpinr11 ocfar<4:0> uart1 receive u1rx rpinr18 u1rxr<4:0> uart1 clear-to-send u1cts rpinr18 u1ctsr<4:0> sdi1 spi data input 1 sdi1 rpinr20 sdi1r<4:0> ( 2 ) sck1 spi clock input 1 sck1 rpinr20 sck1r<4:0> ( 2 ) spi1 slave select input ss1 rpinr21 ss1r<4:0> ( 2 ) note 1: unless otherwise noted, all inputs use the schmitt input buffers. 2: these bits are available in dspic33fj32(gp/mc)10x devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 144 ? 2011-2014 microchip technology inc. 10.4.2.2 output mapping in contrast to the inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. in this case, a control register associated with a particular pin dictates the peripheral output to be mapped. the rporx registers are used to control out- put mapping. like the rpinrx registers, each register contains sets of 5-bit fields, with each set associated with one rpn pin (see register 10-11 through register 10-23 ). the value of the bit field corresponds to one of the peripherals and that peripheral?s output is mapped to the pin (see table 10-2 and figure 10-3 ). the list of peripherals for output mapping also includes a null value of ? 00000 ? because of the mapping technique. this permits any given pin to remain unconnected from the output of any of the pin selectable peripherals. figure 10-3: multiplexing of remappable output for rpn table 10-2: output selection for remappable pin (rpn) 0 3 rpnr<4:0> default u1tx output enable u1rts output enable 4 19 oc2 output enable 0 3 default u1tx output u1rts output 4 19 oc2 output output enable output data rpn function rpnr<4:0> output name null 00000 rpn tied to default port pin c1out 00001 rpn tied to comparator 1 output c2out 00010 rpn tied to comparator 2 output u1tx 00011 rpn tied to uart1 transmit u1rts 00100 rpn tied to uart1 ready-to-send sck1 01000 rpn tied to spi clock ( 1 ) sdo1 00111 rpn tied to spi data output ( 1 ) ss1 01001 rpn tied to spi1 slave select output ( 1 ) oc1 10010 rpn tied to output compare 1 oc2 10011 rpn tied to output compare 2 ctpls 11101 rpn tied to ctmu pulse output c3out 11110 rpn tied to comparator 3 output note 1: this function is available in dspic33fj32(gp/mc)10x devices only.
? 2011-2014 microchip technology inc. ds70000652f-page 145 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 10.4.3 controlling configuration changes because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/ mc)101/102/104 devices include three features to prevent alterations to the peripheral map: ? control register lock sequence ? continuous state monitoring ? configuration bit pin select lock 10.4.3.1 control register lock under normal operation, writes to the rpinrx and rporx registers are not allowed. attempted writes appear to execute normally, but the contents of the registers remain unchanged. to change these regis- ters, they must be unlocked in hardware. the register lock is controlled by the iolock bit (osccon<6>). setting iolock prevents writes to the control registers; clearing iolock allows writes. to set or clear iolock, a specific command sequence must be executed: 1. write 0x46 to osccon<7:0>. 2. write 0x57 to osccon<7:0>. 3. clear (or set) iolock as a single operation. unlike the similar sequence with the oscillator?s lock bit, iolock remains in one state until changed. this allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. 10.4.3.2 continuous state monitoring in addition to being protected from direct writes, the contents of the rpinrx and rporx registers are constantly monitored in hardware by shadow registers. if an unexpected change in any of the registers occurs (such as cell disturbances caused by esd or other external events), a configuration mismatch reset will be triggered. 10.4.3.3 configuration bit pin select lock as an additional level of safety, the device can be configured to prevent more than one write session to the rpinrx and rporx registers. the iol1way (fosc<5>) configuration bit blocks the iolock bit from being cleared after it has been set once. if iolock remains set, the register unlock procedure will not execute and the peripheral pin select control registers cannot be written to. the only way to clear the bit and re-enable peripheral remapping is to perform a device reset. in the default (unprogrammed) state, iol1way is set, restricting users to one write session. programming iol1way allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. note: mplab ? c30 provides built-in c language functions for unlocking the osccon register: __builtin_write_oscconl(value) __builtin_write_oscconh(value) see mplab ide help for more information.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 146 ? 2011-2014 microchip technology inc. 10.5 i/o helpful tips 1. in some cases, certain pins, as defined in section 26.0 ?electrical characteristics? , table 26-11 under ?injection current?, have internal protection diodes to v dd and v ss . the term, ?injection current?, is also referred to as ?clamp current?. on designated pins, with suffi- cient external current limiting precautions by the user, i/o pin input voltages are allowed to be greater or less than the data sheet absolute maximum ratings with nominal v dd , with respect to the v ss and v dd supplies. note that when the user application forward biases either of the high or low side internal input clamp diodes, that the resulting current being injected into the device, that is clamped internally by the v dd and v ss power rails, may affect the adc accuracy by four to six counts. 2. i/o pins that are shared with any analog input pin, (i.e., anx), are always analog pins by default after any reset. consequently, any pin(s) configured as an analog input pin, automatically disables the digital input pin buffer. as such, any attempt to read a digital input pin will always return a ? 0 ? regardless of the digital logic level on the pin if the analog pin is configured. to use a pin as a digital i/o pin on a shared anx pin, the user application needs to configure the adc1 port configuration low (ad1pcfgl) register in the adc module, by setting the appropriate bit that corresponds to that i/o port pin, to a ? 1 ?. on devices with more than one adc, both analog pin configurations for both adc modules must be configured as a digital i/o pin for that pin to function as a digital i/o pin. 3. most i/o pins have multiple functions. referring to the device pin diagrams in the data sheet, the priorities of the functions allocated to any pins are indicated by reading the pin name from left-to-right. the left most function name takes precedence over any function to its right in the naming convention. for example: an16/t2ck/t7ck/rc1. this indi- cates that an16 is the highest priority in this example and will supersede all other functions to its right in the list. those other functions to its right, even if enabled, would not work as long as any other function to its left was enabled. this rule applies to all of the functions listed for a given pin. 4. each cn pin has a configurable internal weak pull-up resistor. the pull-ups act as a current source connected to the pin and eliminates the need for external resistors in certain applica- tions. the internal pull-up is to ~(v dd ? 0.8), not v dd . this is still above the minimum v ih of cmos and ttl devices. 5. when driving leds directly, the i/o pin can source or sink more current than what is specified in the v oh /i oh and v ol /i ol dc characteristic specification. the respective i oh and i ol current rating only applies to maintaining the correspond- ing output at or above the v oh and at or below the v ol levels. however, for leds unlike digital inputs of an externally connected device, they are not governed by the same minimum v ih /v il levels. an i/o pin output can safely sink or source any current less than that listed in the absolute maximum rating section of the data sheet. for example: v oh = 2.4v @ i oh = -6 ma and v dd = 3.3v the maximum output current sourced by any 6 ma i/o pin = 15 ma. led source current < 15 ma is technically permitted. refer to the v oh /i oh specifications in section 26.0 ?electrical characteristics? for additional information. 10.6 i/o resources many useful resources are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 10.6.1 key resources ? ?i/o ports? (ds70193) in the ?dspic33/pic24 family reference manual? ? code samples ? application notes ? software libraries ? webinars ? all related ?dspic33/pic24 family reference manual? sections ? development tools note: although it is not possible to use a digital input pin when its analog function is enabled, it is possible to use the digital i/o output function, trisx = 0x0 , while the analog function is also enabled. however, this is not recommended, particularly if the analog input is connected to an external analog voltage source, which would create signal contention between the analog signal and the output pin driver. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554109
? 2011-2014 microchip technology inc. ds70000652f-page 147 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 10.7 peripheral pin select registers the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family of devices implements up to 23 registers for remappable peripheral configuration. note: input and output register values can only be changed if iolock (osccon<6>) = 0 . see section 10.4.3.1 ?control register lock? for a specific command sequence. register 10-1: rpinr0: peripheral pin select input register 0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? int1r4 int1r3 int1r2 int1r1 int1r0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 int1r<4:0>: assign external interrupt 1 (intr1) to the corresponding rpn pin bits 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-0 unimplemented: read as ? 0 ?
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 148 ? 2011-2014 microchip technology inc. register 10-2: rpinr1: peripheral pin select input register 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? int2r4 int2r3 int2r2 int2r1 int2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 int2r<4:0>: assign external interrupt 2 (intr2) to the corresponding rpn pin bits 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0
? 2011-2014 microchip technology inc. ds70000652f-page 149 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 10-3: rpinr3: peripheral pin select input register 3 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? t3ckr4 t3ckr3 t3ckr2 t3ckr1 t3ckr0 bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? t2ckr4 t2ckr3 t2ckr2 t2ckr1 t2ckr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 t3ckr<4:0>: assign timer3 external clock (t3ck) to the corresponding rpn pin bits 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 t2ckr<4:0>: assign timer2 external clock (t2ck) to the corresponding rpn pin bits 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 150 ? 2011-2014 microchip technology inc. register 10-4: rpinr4: peripheral pin select input register 4 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?t5ckr4 ( 1 ) t5ckr3 ( 1 ) t5ckr2 ( 1 ) t5ckr1 ( 1 ) t5ckr0 ( 1 ) bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?t4ckr4 ( 1 ) t4ckr3 ( 1 ) t4ckr2 ( 1 ) t4ckr1 ( 1 ) t4ckr0 ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 t5ckr<4:0>: assign timer5 external clock (t5ck) to the corresponding rpn pin bits ( 1 ) 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 t4ckr<4:0>: assign timer4 external clock (t4ck) to the corresponding rpn pin bits ( 1 ) 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 note 1: these bits are available in dspic33fj32(gp/mc)10x devices only.
? 2011-2014 microchip technology inc. ds70000652f-page 151 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 10-5: rpinr7: peripheral pin select input register 7 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ic2r4 ic2r3 ic2r2 ic2r1 ic2r0 bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ic1r4 ic1r3 ic1r2 ic1r1 ic1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 ic2r<4:0>: assign input capture 2 (ic2) to the corresponding rpn pin bits 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 ic1r<4:0>: assign input capture 1 (ic1) to the corresponding rpn pin bits 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 152 ? 2011-2014 microchip technology inc. register 10-6: rpinr8: peripheral pin select input register 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ic3r4 ic3r3 ic3r2 ic3r1 ic3r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 ic3r<4:0>: assign input capture 3 (ic3) to the corresponding rpn pin bits 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0
? 2011-2014 microchip technology inc. ds70000652f-page 153 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 10-7: rpinr11: peripheral pin select input register 11 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ocfar4 ocfar3 ocfar2 ocfar1 ocfar0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 ocfar<4:0>: assign output capture a (ocfa) to the corresponding rpn pin bits 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 154 ? 2011-2014 microchip technology inc. register 10-8: rpinr18: peripheral pin select input register 18 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? u1ctsr4 u1ctsr3 u1ctsr2 u1ctsr1 u1ctsr0 bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? u1rxr4 u1rxr3 u1rxr2 u1rxr1 u1rxr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 u1ctsr<4:0>: assign uart1 clear-to-send (u1cts ) to the corresponding rpn pin bits 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 u1rxr<4:0>: assign uart1 receive (u1rx) to the corresponding rpn pin bits 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0
? 2011-2014 microchip technology inc. ds70000652f-page 155 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 10-9: rpinr20: peripheral pin select input register 20 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?sck1r4 ( 1 ) sck1r3 ( 1 ) sck1r2 ( 1 ) sck1r1 ( 1 ) sck1r0 ( 1 ) bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?sdi1r4 ( 1 ) sdi1r3 ( 1 ) sdi1r2 ( 1 ) sdi1r1 ( 1 ) sdi1r0 ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 sck1r<4:0>: assign spi1 clock input (sck1in) to the corresponding rpn pin bits ( 1 ) 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 sdi1r<4:0>: assign spi1 data input (sdi1) to the corresponding rpn pin bits ( 1 ) 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 note 1: these bits are available in dspic33fj32(gp/mc)10x devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 156 ? 2011-2014 microchip technology inc. register 10-10: rpinr21: peripheral pin select input register 21 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ss1r4 ss1r3 ss1r2 ss1r1 ss1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 ss1r<4:0>: assign spi1 slave select input (ss1in) to the corresponding rpn pin bits 11111 = input tied to v ss 11110 = reserved . . . 11010 = reserved 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0
? 2011-2014 microchip technology inc. ds70000652f-page 157 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 10-11: rpor0: peripheral pin select output register 0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp1r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp0r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp1r<4:0>: peripheral output function is assigned to rp1 output pin bits (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp0r<4:0>: peripheral output function is assigned to rp0 output pin bits (see table 10-2 for peripheral function numbers) register 10-12: rpor1: peripheral pin select output register 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp3r<4:0> ( 1 ) bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp2r<4:0> ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp3r<4:0>: peripheral output function is assigned to rp3 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp2r<4:0>: peripheral output function is assigned to rp2 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) note 1: these bits are not available in dspic33fjxx(gp/mc)101 devices.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 158 ? 2011-2014 microchip technology inc. register 10-13: rpor2: peripheral pin select output register 2 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp5r<4:0> ( 1 ) bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp4r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp5r<4:0>: peripheral output function is assigned to rp5 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp4r<4:0>: peripheral output function is assigned to rp4 output pin bits (see table 10-2 for peripheral function numbers) note 1: these bits are not available in dspic33fj(16/32)(gp/mc)101 devices. register 10-14: rpor3: peripheral pin select output register 3 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp7r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp6r<4:0> ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp7r<4:0>: peripheral output function is assigned to rp7 output pin bits (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp6r<4:0>: peripheral output function is assigned to rp6 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) note 1: these bits are not available in dspic33fj(16/32)(gp/mc)101 devices.
? 2011-2014 microchip technology inc. ds70000652f-page 159 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 10-15: rpor4: peripheral pin select output register 4 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp9r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp8r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp9r<4:0>: peripheral output function is assigned to rp9 output pin bits (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp8r<4:0>: peripheral output function is assigned to rp8 output pin bits (see table 10-2 for peripheral function numbers) register 10-16: rpor5: peripheral pin select output register 5 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp11r<4:0> ( 1 ) bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp10r<4:0> ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp11r<4:0>: peripheral output function is assigned to rp11 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp10r<4:0>: peripheral output function is assigned to rp10 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) note 1: these bits are not available in dspic33fjxx(gp/mc)101 devices.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 160 ? 2011-2014 microchip technology inc. register 10-17: rpor6: peripheral pin select output register 6 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp13r<4:0> ( 1 ) bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp12r<4:0> ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp13r<4:0>: peripheral output function is assigned to rp13 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp12r<4:0>: peripheral output function is assigned to rp12 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) note 1: these bits are not available in dspic33fjxxgp101 devices. register 10-18: rpor7: peripheral pin select output register 7 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp15r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp14r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp15r<4:0>: peripheral output function is assigned to rp15 output pin bits (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp14r<4:0>: peripheral output function is assigned to rp14 output pin bits (see table 10-2 for peripheral function numbers)
? 2011-2014 microchip technology inc. ds70000652f-page 161 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 10-19: rpor8: peripheral pin select output register 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp17r<4:0> ( 1 ) bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp16r<4:0> ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp17r<4:0>: peripheral output function is assigned to rp17 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp16r<4:0>: peripheral output function is assigned to rp16 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) note 1: these bits are available in dspic33fj32(gp/mc)104 devices only. register 10-20: rpor9: peripheral pin select output register 9 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp19r<4:0> ( 1 ) bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp18r<4:0> ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp19r<4:0>: peripheral output function is assigned to rp19 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp18r<4:0>: peripheral output function is assigned to rp18 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) note 1: these bits are available in dspic33fj32(gp/mc)104 devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 162 ? 2011-2014 microchip technology inc. register 10-21: rpor10: peripheral pin select output register 10 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp21r<4:0> ( 1 ) bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp20r<4:0> ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp21r<4:0>: peripheral output function is assigned to rp21 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp20r<4:0>: peripheral output function is assigned to rp20 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) note 1: these bits are available in dspic33fj32(gp/mc)104 devices only. register 10-22: rpor11: peripheral pin select output register 11 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp23r<4:0> ( 1 ) bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp22r<4:0> ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp23r<4:0>: peripheral output function is assigned to rp23 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp22r<4:0>: peripheral output function is assigned to rp22 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) note 1: these bits are available in dspic33fj32(gp/mc)104 devices only.
? 2011-2014 microchip technology inc. ds70000652f-page 163 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 \ register 10-23: rpor12: peripheral pin select output register 12 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp25r<4:0> ( 1 ) bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp24r<4:0> ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp25r<4:0>: peripheral output function is assigned to rp25 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp24r<4:0>: peripheral output function is assigned to rp24 output pin bits ( 1 ) (see table 10-2 for peripheral function numbers) note 1: these bits are available in dspic33fj32(gp/mc)104 devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 164 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 165 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 11.0 timer1 the timer1 module is a 16-bit timer, which can serve as the time counter for the real-time clock (rtc) or operate as a free-running interval timer/counter. timer1 can operate in three modes: ?16-bit timer ? 16-bit synchronous counter ? 16-bit asynchronous counter timer1 also supports these features: ? timer gate operation ? selectable prescaler settings ? timer operation during cpu idle and sleep modes ? interrupt on 16-bit period register match or falling edge of external gate signal figure 11-1 presents a block diagram of the 16-bit timer module. to configure timer1 for operation: 1. load the timer value into the tmr1 register. 2. load the timer period value into the pr1 register. 3. select the timer prescaler ratio using the tckps<1:0> bits in the t1con register. 4. set the clock and gating modes using the tcs and tgate bits in the t1con register. 5. set or clear the tsync bit in t1con to select synchronous or asynchronous operation. 6. if interrupts are required, set the timer1 inter- rupt enable bit, t1ie. use the timer1 interrupt priority bits, t1ip<2:0>, to set the interrupt priority. 7. set the ton bit (= 1 ) in the t1con register. figure 11-1: 16-bit time r1 module block diagram note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to com- plement the information in this data sheet, refer to ?timers? (ds70205) in the ?dspic33/pic24 family reference man- ual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. ton sosci sosco/ pr1 set t1if equal comparator tmr1 reset soscen 1 0 tsync q qd ck tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 t1ck tcs tgate sync gate sync 1x 01 00
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 166 ? 2011-2014 microchip technology inc. 11.1 timer1 control register register 11-1: t1con: timer1 control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ( 1 ) ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 ? tgate tckps1 tckps0 ? tsync tcs ( 1 ) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer1 on bit ( 1 ) 1 = starts 16-bit timer1 0 = stops 16-bit timer1 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: timer1 stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer1 gated time accumulation enable bit when t c s = 1 : this bit is ignored. when t c s = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0> timer1 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 unimplemented: read as ? 0 ? bit 2 tsync: timer1 external clock input synchronization select bit when tcs = 1 : 1 = synchronizes external clock input 0 = does not synchronize external clock input when tcs = 0 : this bit is ignored. bit 1 tcs: timer1 clock source select bit ( 1 ) 1 = external clock from pin, t1ck (on the rising edge) 0 = internal clock (f cy ) bit 0 unimplemented: read as ? 0 ? note 1: when tcs = 1 and ton = 1 , writes to the tmr1 register are inhibited from the cpu.
? 2011-2014 microchip technology inc. ds70000652f-page 167 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 12.0 timer2/3 and timer4/5 timer2/3 and timer4/5 have three 2-bit timers that can also be configured as two independent 16-bit timers with selectable operating modes. as a 32-bit timer, timer2/3 and timer4/5 permit operation in three modes: ? two independent 16-bit timers (e.g., timer2 and timer3 or timer4 and timer5) with all 16-bit operating modes (except asynchronous counter mode) ? single 32-bit timer (timer2/3 and timer4/5) ? single 32-bit synchronous counter (timer2/3 and timer4/5) timer2/3 and timer4/5 also support: ? timer gate operation ? selectable prescaler settings ? timer operation during idle and sleep modes ? interrupt on a 32-bit period register match ? time base for input capture and output compare modules (timer2 and timer3 only) ? adc1 event trigger (timer2/3 only) individually, all eight of the 16-bit timers can function as synchronous timers or counters. they also offer the features listed above, except for the event trigger. the operating modes and enabled features are determined by setting the appropriate bit(s) in the t2con, t3con, t4con and t5con registers (see register 12-1 through register 12-4 ). for 32-bit timer/counter operation, timer2/4 is the least significant word (lsw) and timer3/5 is the most significant word (msw) of the 32-bit timers. 12.1 32-bit operation to configure timer2/3 and timer4/5 for 32-bit operation: 1. set the t32 control bit. 2. select the prescaler ratio for timer2 or timer4 using the tckps<1:0> bits. 3. set the clock and gating modes using the corresponding tcs and tgate bits. 4. load the timer period value. pr3/pr5 contains the msw of the value, while pr2/pr4 contains the least significant word (lsw). 5. if interrupts are required, set the timer3 (or timer5) interrupt enable bit, t3ie (or t5ie). use the priority bits, t3ip<2:0> or t5ip<2:0>, to set the interrupt priority. while timer2/timer4 controls the timer, the interrupt appears as a timer3/timer5 interrupt. 6. set the corresponding ton bit. the timer value at any point is stored in the register pair, tmr3:tmr2 or tmr5:tmr4, which always contains the msw of the count, while tmr2 or tmr4 contains the lsw. 12.2 16-bit operation to configure any of the timers for individual 16-bit operation: 1. clear the t32 bit corresponding to that timer. 2. select the timer prescaler ratio using the tckps<1:0> bits. 3. set the clock and gating modes using the tcs and tgate bits. 4. load the timer period value into the prx register. 5. if interrupts are required, set the timerx interrupt enable bit, txie. use the priority bits, txip<2:0>, to set the interrupt priority. 6. set the ton bit. note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to com- plement the information in this data sheet, refer to ?timers? (ds70205) in the ?dspic33/pic24 family reference man- ual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. note 1: timer4 and timer5 are available in dspic33fj32(gp/mc10x) devices only. note: for 32-bit operation, t3con and t5con control bits are ignored. only t2con and t4con control bits are used for setup and control. timer2 and timer4 clock and gate inputs are used for the 32-bit timer modules, but an interrupt is generated with the timer3 and timer5 interrupt flags.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 168 ? 2011-2014 microchip technology inc. figure 12-1: timer2/3 and timer4/5 (32-bit) block diagram ( 1 , 3 , 4 ) set txif equal comparator prx pry reset lsb msb note 1: the 32-bit timer control bit, t32, must be set for 32-bit timer/counter operation. all control bits are respective to the txcon register. 2: the adc event trigger is available only on timer2/3. 3: timer4/5 is available in dspi c33fj32(gp/mc)10x devices only. 4: where ?x? or ?y? is present , x = 2 or 4; y = 3 or 5. data bus<15:0> tmrxhld read tmrx/tmry write tmrx/tmry 16 16 16 q q d ck tgate 0 1 ton tckps<1:0> 2 t cy tcs 1x 01 tgate 00 txck adc event trigger (2) gate sync prescaler 1, 8, 64, 256 sync tmrx tmry 16 to ctmu filter
? 2011-2014 microchip technology inc. ds70000652f-page 169 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 12-2: timer2 and time r4 (16-bit) block diagram ( 1 ) figure 12-3: timer3 and time r5 (16-bit) block diagram ( 1 ) ton tckps<1:0> prescaler 1, 8, 64, 256 2 t cy tcs tgate txck set txif equal comparator reset q qd ck tgate 1 0 gate sync 1x 01 00 sync to ctmu filter note 1: timer4 is available in dspi c33fj32(gp/mc)10x devices only. tmrx prx prescaler (/n) gate sync tgate tcs 00 10 x1 tmrx prx f cy tgate set txif flag 0 1 sync tckps<1:0> equal reset txck adc soc trigger prescaler (/n) tckps<1:0> to ctmu filter note 1: timer5 is available in dspi c33fj32(gp/mc)10x devices only. falling edge detect comparator
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 170 ? 2011-2014 microchip technology inc. 12.3 timer2/3 and timer4/5 control registers register 12-1: t2con: ti mer2 control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 ? tgate tckps1 tckps0 t32 ?tcs ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer2 on bit when t32 = 1 : 1 = starts 32-bit timer2/3 0 = stops 32-bit timer2/3 when t32 = 0 : 1 = starts 16-bit timer2 0 = stops 16-bit timer2 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: timer2 stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer2 gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timer2 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 t32: 32-bit timer mode select bit 1 = timer2 and timer3 form a single 32-bit timer 0 = timer2 and timer3 act as two 16-bit timers bit 2 unimplemented: read as ? 0 ? bit 1 tcs: timer2 clock source select bit 1 = external clock from pin, t2ck (on the rising edge) 0 = internal clock (f cy ) bit 0 unimplemented: read as ? 0 ?
? 2011-2014 microchip technology inc. ds70000652f-page 171 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 12-2: t3con: ti mer3 control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ( 2 ) ?tsidl ( 1 ) ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 ? tgate ( 2 ) tckps1 ( 2 ) tckps0 ( 2 ) ? ?tcs ( 2 ) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer3 on bit ( 2 ) 1 = starts 16-bit timer3 0 = stops 16-bit timer3 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: timer3 stop in idle mode bit ( 1 ) 1 = discontinues timer operation when device enters idle mode 0 = continues timer operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer3 gated time accumulation enable bit ( 2 ) when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timer3 input clock prescale select bits ( 2 ) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3-2 unimplemented: read as ? 0 ? bit 1 tcs: timer3 clock source select bit ( 2 ) 1 = external clock from t3ck pin 0 = internal clock (f osc /2) bit 0 unimplemented: read as ? 0 ? note 1: when 32-bit timer operation is enabled (t32 = 1 ) in the timer2 control register (t2con<3>), the tsidl bit must be cleared to operate the 32-bit timer in idle mode. 2: when the 32-bit timer operation is enabled (t32 = 1 ) in the timer2 control register (t2con<3>), these bits have no effect.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 172 ? 2011-2014 microchip technology inc. register 12-3: t4con: ti mer4 control register ( 1 ) r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 ? tgate tckps1 tckps0 t32 ?tcs ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer4 on bit when t32 = 1 : 1 = starts 32-bit timer4/5 0 = stops 32-bit timer4/5 when t32 = 0 : 1 = starts 16-bit timer4 0 = stops 16-bit timer4 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: timer4 stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer4 gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timer4 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 t32: 32-bit timer mode select bit 1 = timer4 and timer5 form a single 32-bit timer 0 = timer4 and timer5 act as two 16-bit timers bit 2 unimplemented: read as ? 0 ? bit 1 tcs: timer4 clock source select bit 1 = external clock from pin, t4ck (on the rising edge) 0 = internal clock (f cy ) bit 0 unimplemented: read as ? 0 ? note 1: this register is available in dspic33fj32(gp/mc)10x devices only.
? 2011-2014 microchip technology inc. ds70000652f-page 173 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 12-4: t5con: ti mer5 control register ( 1 ) r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ( 3 ) ?tsidl ( 2 ) ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 ? tgate ( 3 ) tckps1 ( 3 ) tckps0 ( 3 ) ? ?tcs ( 3 ) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer5 on bit ( 3 ) 1 = starts 16-bit timer3 0 = stops 16-bit timer3 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: timer5 stop in idle mode bit ( 2 ) 1 = discontinues timer operation when device enters idle mode 0 = continues timer operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer5 gated time accumulation enable bit ( 3 ) when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timer5 input clock prescale select bits ( 3 ) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3-2 unimplemented: read as ? 0 ? bit 1 tcs: timer5 clock source select bit ( 3 ) 1 = external clock from t5ck pin 0 = internal clock (f osc /2) bit 0 unimplemented: read as ? 0 ? note 1: this register is available in dspic33fj32(gp/mc)10x devices only. 2: when 32-bit timer operation is enabled (t32 = 1 ) in the timer4 control register (t4con<3>), the tsidl bit must be cleared to operate the 32-bit timer in idle mode. 3: when the 32-bit timer operation is enabled (t32 = 1 ) in the timer4 control register (t4con<3>), these bits have no effect.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 174 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 175 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 13.0 input capture the input capture module is useful in applications requiring frequency (period) and pulse measurement. the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices support up to three input capture channels. the input capture module captures the 16-bit value of the selected time base register when an event occurs on the icx pin. the events that cause a capture event are listed below in three categories: 1. simple capture event modes: ? capture timer value on every falling edge of input at icx pin ? capture timer value on every rising edge of input at icx pin 2. capture timer value on every edge (rising and falling). 3. prescaler capture event modes: ? capture timer value on every 4th rising edge of input at icx pin ? capture timer value on every 16th rising edge of input at icx pin each input capture channel can select one of two 16-bit timers (timer2 or timer3) for the time base. the selected timer can use either an internal or external clock. other operational features include: ? device wake-up from capture pin during cpu sleep and idle modes ? interrupt on input capture event ? 4-word fifo buffer for capture values: - interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled ? use of input capture to provide additional sources of external interrupts figure 13-1: input capture x block diagram note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to ?input capture? (ds70198) in the ?dspic33/pic24 family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. icxbuf icx pin icm<2:0> (icxcon<2:0>) mode select 3 set flag icxif (in ifsn register) tmr2 tmr3 edge detection logic 16 16 ici<1:0> icov, icbne (icxcon<4:3>) icxcon interrupt logic system bus from 16-bit timers ictmr (icxcon<7>) fifo prescaler counter (1, 4, 16) and clock synchronizer note: an ?x? in a signal, register or bit name denotes the number of the input capture channel. fifo r/w logic 10
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 176 ? 2011-2014 microchip technology inc. 13.1 input capture control register register 13-1: icxcon: input capture x control register u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?icsidl ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-0, hc r-0, hc r/w-0 r/w-0 r/w-0 ictmr ici1 ici0 icov icbne icm2 icm1 icm0 bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 icsidl: input capture x stop in idle control bit 1 = input capture x module will halt in cpu idle mode 0 = input capture x module will continue to operate in cpu idle mode bit 12-8 unimplemented: read as ? 0 ? bit 7 ictmr: input capture x timer select bits 1 = tmr2 contents are captured on a capture event 0 = tmr3 contents are captured on a capture event bit 6-5 ici<1:0>: select number of captures per interrupt bits 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture x overflow status flag bit (read-only) 1 = input capture x overflow occurred 0 = no input capture x overflow occurred bit 3 icbne: input capture x buffer empty status bit (read-only) 1 = input capture x buffer is not empty, at least one more capture value can be read 0 = input capture x buffer is empty bit 2-0 icm<2:0>: input capture x mode select bits 111 = input capture x functions as an interrupt pin only when device is in sleep or idle mode (rising edge detect only, all other control bits are not applicable) 110 = unused (module is disabled) 101 = capture mode, every 16th rising edge 100 = capture mode, every 4th rising edge 011 = capture mode, every rising edge 010 = capture mode, every falling edge 001 = capture mode, every edge, rising and falling (ici<1:0> bits do not control interrupt generation for this mode) 000 = input capture x module is turned off
? 2011-2014 microchip technology inc. ds70000652f-page 177 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 14.0 output compare the output compare module can select either timer2 or timer3 for its time base. the module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. the state of the output pin changes when the timer value matches the output compare control register value. the output compare module generates either a single output pulse, or a sequence of output pulses, by changing the state of the output pin on the compare match events. the output compare module can also generate interrupts on compare match events. the output compare module has multiple operating modes: ? active-low one-shot mode ? active-high one-shot mode ? toggle mode ? delayed one-shot mode ? continuous pulse mode ? pwm mode without fault protection ? pwm mode with fault protection figure 14-1: output compare x module block diagram note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to com- plement the information in this data sheet, refer to ?output compare? (ds70209) in the ?dspic33/pic24 family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. ocxr comparator output logic ocm<2:0> ocx set flag bit, ocxif ocxrs mode select 3 octsel 01 16 16 ocfa tmr2 tmr2 q s r tmr3 tmr3 rollover rollover output logic output enable enable 0 1
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 178 ? 2011-2014 microchip technology inc. 14.1 output compare modes configure the output compare modes by setting the appropriate output compare mode bits (ocm<2:0>) in the output compare x control (ocxcon<2:0>) register. table 14-1 lists the different bit settings for the output compare modes. figure 14-2 illustrates the output compare operation for various modes. the user application must disable the associated timer when writing to the output compare control registers to avoid malfunctions. table 14-1: output compare x modes figure 14-2: output compare x operation note: see ?output compare? in the ?dspic33/ pic24 family reference manual? (ds70209) for ocxr and ocxrs register restrictions. ocm<2:0> mode ocx pin initial state ocx interrupt generation 000 module disabled controlled by gpio register ? 001 active-low one-shot 0 ocx rising edge 010 active-high one-shot 1 ocx falling edge 011 toggle current output is maintained ocx rising and falling edge 100 delayed one-shot 0 ocx falling edge 101 continuous pulse 0 ocx falling edge 110 pwm without fault protection 0 , if ocxr is zero 1 , if ocxr is non-zero no interrupt 111 pwm with fault protection 0 , if ocxr is zero 1 , if ocxr is non-zero ocfa falling edge for oc1 to oc4 ocxrs tmry ocxr timer is reset on period match continuous pulse mode (ocm<2:0> = 101 ) pwm mode (ocm<2:0> = 110 or 111 ) active-low one-shot (ocm<2:0> = 001 ) active-high one-shot (ocm<2:0> = 010 ) toggle mode (ocm<2:0> = 011 ) delayed one-shot (ocm<2:0> = 100 ) output compare mode enabled
? 2011-2014 microchip technology inc. ds70000652f-page 179 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 14.2 output compare control register register 14-1: ocxcon: output compare x control register u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?ocsidl ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r-0, hc r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ocflt octsel ocm2 ocm1 ocm0 bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ocsidl: output compare x stop in idle mode control bit 1 = output compare x will halt in cpu idle mode 0 = output compare x will continue to operate in cpu idle mode bit 12-5 unimplemented: read as ? 0 ? bit 4 ocflt: pwm fault condition status bit 1 = pwm fault condition has occurred (cleared in hardware only) 0 = no pwm fault condition has occurred (this bit is only used when ocm<2:0> = 111 .) bit 3 octsel: output compare x timer selection bit 1 = timer3 is the clock source for output compare x 0 = timer2 is the clock source for output compare x bit 2-0 ocm<2:0>: output compare x mode select bits 111 = pwm mode on ocx, fault pin is enabled 110 = pwm mode on ocx, fault pin is disabled 101 = initializes ocx pin low, generates continuous output pulses on ocx pin 100 = initializes ocx pin low, generates single output pulse on ocx pin 011 = compare event toggles ocx pin 010 = initializes ocx pin high, compare event forces ocx pin low 001 = initializes ocx pin low, compare event forces ocx pin high 000 = output compare x channel is disabled
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 180 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 181 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 15.0 motor control pwm module the dspic33fj16mc10x devices have a 6-channel pulse-width modulation (pwm) module. the pwm module has the following features: ? up to 16-bit resolution ? on-the-fly pwm frequency changes ? edge-aligned and center-aligned output modes ? single pulse generation mode ? interrupt support for asymmetrical updates in center-aligned mode ? output override control for electrically commutative motor (ecm) operation or bldc ? special event comparator for scheduling other peripheral events ? fault pins to optionally drive each of the pwm output pins to a defined state ? duty cycle updates configurable to be immediate or synchronized to the pwm time base 15.1 pwm1: 6-channel pwm module this module simplifies the task of generating multiple synchronized pwm outputs. the following power and motion control applications are supported by the pwm module: ? 3-phase ac induction motor ? switched reluctance (sr) motor ? brushless dc (bldc) motor ? uninterruptible power supply (ups) this module contains three duty cycle generators, numbered 1 through 3. the module has six pwm output pins, numbered pwm1h1/pwm1l1 through pwm1h3/pwm1l3. the six i/o pins are grouped into high/low numbered pairs, denoted by the suffix h or l, respectively. for complementary loads, the low pwm pins are always the complement of the corresponding high i/o pin. note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to ?motor control pwm? (ds70187) in the ? dspic33/pic24 family reference manual? , which is available on the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 182 ? 2011-2014 microchip technology inc. figure 15-1: 6-channel pwm mo dule block diagram (pwm1) p1dc3 p1dc3 buffer pwm1con1 pwm1con2 p1tper comparator comparator channel 3 dead-time generator and p1tcon p1secmp special event trigger p1ovdcon pwm enable and mode sfrs pwm manual control sfr channel 2 dead-time generator and channel 1 dead-time generator and pwm generator 2 (1) pwm generator 1 (1) pwm generator 3 sevtdir ptdir p1dtcon1 dead-time control sfrs pwm1l1 pwm1h1 pwm1l2 pwm1h2 note 1: the details of pwm generator 1 and 2 are not shown for clarity. 2: on dspic33fj16mc101 (20-pin) devices, the flta1 pin is supported, but requires an external pull-down resistor for correct functionality. 3: on dspic33fj16mc102 (28-pin) devices, the flta1 and fltb1 pins are supported and do not require an external pull-down resistor. pwm1l3 pwm1h3 p1dtcon2 p1fltacon fault a pin control sfrs pwm time base output driver block flta1 (2,3) override logic override logic override logic special event postscaler p1tper buffer p1tmr p1fltbcon fault b pin control sfrs fltb1 (3) comparator 16-bit data bus
? 2011-2014 microchip technology inc. ds70000652f-page 183 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 15.2 pwm faults the motor control pwm module incorporates up to two fault inputs, flta1 and fltb1 . these fault inputs are implemented with class b safety features. these features ensure that the pwm outputs enter a safe state when either of the fault inputs is asserted. the flta1 and fltb1 pins, when enabled and having ownership of a pin, also enable a soft internal pull-down resistor. the soft pull-down provides a safety feature by automatically asserting the fault should a break occur in the fault signal connection. the implementation of internal pull-down resistors is dependent on the device variant. table 15-1 describes which devices and pins implement the internal pull-down resistors. table 15-1: internal pull-down resistors on pwm fault pins on devices without internal pull-downs on the fault pin, it is recommended to connect an external pull-down resistor for class b safety features. 15.2.1 pwm faults at reset during any reset event, the pwm module maintains ownership of both pwm fault pins. at reset, both faults are enabled in latched mode to guarantee the fail-safe power-up of the application. the application software must clear both of the pwm faults before enabling the motor control pwm module. the fault condition must be cleared by the external cir- cuitry driving the fault input pin high and clearing the fault interrupt flag. after the fault pin condition has been cleared, the pwm module restores the pwm output signals on the next pwm period or half-period boundary. refer to ?motor control pwm? (ds70187) in the ? dspic33/pic24 family reference manual? for more information on the pwm faults. 15.3 write-protected registers on dspic33fj(16/32)mc10x devices, write protection is implemented for the pwmxcon1, pxfltacon and pxfltbcon registers. the write protection feature prevents any inadvertent writes to these registers. the write protection feature can be controlled by the pwmlock configuration bit in the foscsel config- uration register. the default state of the write protection feature is enabled (pwmlock = 1 ). the write protec- tion feature can be disabled by configuring pwmlock (foscsel<6>) = 0 . the user application can gain access to these locked registers either by configuring the pwmlock bit (foscsel<6>) = 0 or by performing the unlock sequence. to perform the unlock sequence, the user application must write two consecutive values (0xabcd and 0x4321) to the pwmxkey register to perform the unlock operation. the write access to the pwmxcon1, pxfltacon or pxfltbcon registers must be the next sfr access following the unlock process. there can be no other sfr accesses during the unlock process and subsequent write access. to write to all registers, the pwmxcon1, pxfltacon and pxfltbcon registers require three unlock operations. the correct unlocking sequence is described in example 15-1 and example 15-2 . device fault pin internal pull-down implemented? dspic33fjxxmc101 flta1 no dspic33fjxxmc102 flta1 yes fltb1 yes dspic33fj32mc104 flta1 yes fltb1 yes note: the number of pwm faults mapped to the device pins depend on the specific variant. regardless of the variant, both faults will be enabled during any reset event. the application must clear both flta1 and fltb1 before enabling the motor control pwm module. refer to the specific device pin diagrams to see which fault pins are mapped to the device pins.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 184 ? 2011-2014 microchip technology inc. example 15-1: assembly code for write-protected register unlock and fault clearing sequence example 15-2: c code for wr ite-protected register unlock and fault clearing sequence ; flta1 pin must be pulled high externally in order to clear and disable the fault ; writing to p1fltbcon register requires unlock sequence mov #0xabcd,w10 ; load first unlock key to w10 register mov #0x4321,w11 ; load second unlock key to w11 register mov #0x0000,w0 ; load desired value of p1fltacon register in w0 mov w10, pwm1key ; write first unlock key to pwm1key register mov w11, pwm1key ; write second unlock key to pwm1key register mov w0,p1fltacon ; write desired value to p1fltacon register ; fltb1 pin must be pulled high externally in order to clear and disable the fault ; writing to p1fltbcon register requires unlock sequence mov #0xabcd,w10 ; load first unlock key to w10 register mov #0x4321,w11 ; load second unlock key to w11 register mov #0x0000,w0 ; load desired value of p1fltbcon register in w0 mov w10, pwm1key ; write first unlock key to pwm1key register mov w11, pwm1key ; write second unlock key to pwm1key register mov w0,p1fltbcon ; write desired value to p1fltbcon register ; enable all pwms using pwm1con1 register ; writing to pwm1con1 register requires unlock sequence mov #0xabcd,w10 ; load first unlock key to w10 register mov #0x4321,w11 ; load second unlock key to w11 register mov #0x0077,w0 ; load desired value of pwm1con1 register in w0 mov w10, pwm1key ; write first unlock key to pwm1key register mov w11, pwm1key ; write second unlock key to pwm1key register mov w0,pwm1con1 ; write desired value to pwm1con1 register // flta1 pin must be pulled high externally in order to clear and disable the fault // writing to p1fltacon register requires unlock sequence // use builtin function to write 0x0000 to p1fltacon register __builtin_write_pwmsfr(&p1fltacon, 0x0000, &pwm1key); // fltb1 pin must be pulled high externally in order to clear and disable the fault // writing to p1fltbcon register requires unlock sequence // use builtin function to write 0x0000 to p1fltbcon register __builtin_write_pwmsfr(&p1fltbcon, 0x0000, &pwm1key); // enable all pwms using pwm1con1 register // writing to pwm1con1 register requires unlock sequence // use builtin function to write 0x0077 to pwm1con1 register __builtin_write_pwmsfr(&pwm1con1, 0x0077, &pwm1key);
? 2011-2014 microchip technology inc. ds70000652f-page 185 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 15.4 pwm control registers register 15-1: pxtcon: pwmx time base control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 pten ?ptsidl ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ptops3 ptops2 ptops1 ptops0 ptckps1 ptckps0 ptmod1 ptmod0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 pten: pwmx time base timer enable bit 1 = pwmx time base is on 0 = pwmx time base is off bit 14 unimplemented: read as ? 0 ? bit 13 ptsidl: pwmx time base stop in idle mode bit 1 = pwmx time base halts in cpu idle mode 0 = pwmx time base runs in cpu idle mode bit 12-8 unimplemented: read as ? 0 ? bit 7-4 ptops<3:0>: pwmx time base output postscale select bits 1111 = 1:16 postscale ? ? ? 0001 = 1:2 postscale 0000 = 1:1 postscale bit 3-2 ptckps<1:0>: pwmx time base input clock prescale select bits 11 = pwmx time base input clock period is 64 t cy (1:64 prescale) 10 = pwmx time base input clock period is 16 t cy (1:16 prescale) 01 = pwmx time base input clock period is 4 t cy (1:4 prescale) 00 = pwmx time base input clock period is t cy (1:1 prescale) bit 1-0 ptmod<1:0>: pwmx time base mode select bits 11 = pwmx time base operates in a continuous up/down count mode with interrupts for double pwm updates 10 = pwmx time base operates in a continuous up/down count mode 01 = pwmx time base operates in single pulse mode 00 = pwmx time base operates in a free-running mode
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 186 ? 2011-2014 microchip technology inc. register 15-2: pxtmr: pwmx timer count value register r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ptdir ptmr<14:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ptmr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ptdir: pwmx time base count direction status bit (read-only) 1 = pwmx time base is counting down 0 = pwmx time base is counting up bit 14-0 ptmr <14:0>: pwmx time base register count value bits register 15-3: pxtper: pwmx time base period register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ptper<14:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ptper<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-0 ptper<14:0>: pwmx time base period value bits
? 2011-2014 microchip technology inc. ds70000652f-page 187 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 15-4: pxsecmp: pwmx special event compare register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sevtdir ( 1 ) sevtcmp<14:8> ( 2 ) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sevtcmp<7:0> ( 2 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 sevtdir: special event trigger time base direction bit ( 1 ) 1 = a special event trigger will occur when the pwmx time base is counting down 0 = a special event trigger will occur when the pwmx time base is counting up bit 14-0 sevtcmp<14:0>: special event compare value bits ( 2 ) note 1: sevtdir is compared with ptdir (pxtmr<15>) to generate the special event trigger. 2: pxsecmp<14:0> is compared with pxtmr<14:0> to generate the special event trigger.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 188 ? 2011-2014 microchip technology inc. register 15-5: pwmxcon1: pw mx control register 1 ( 1 ) u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? pmod3 pmod2 pmod1 bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 ? pen3h ( 2 ) pen2h ( 2 ) pen1h ( 2 ) ? pen3l ( 2 ) pen2l ( 2 ) pen1l ( 2 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 pmod<3:1>: pwmx i/o pair mode bits 1 = pwmx i/o pin pair is in the independent pwm output mode 0 = pwmx i/o pin pair is in the complementary output mode bit 7 unimplemented: read as ? 0 ? bit 6-4 pen3h:pen1h: pwmxh i/o enable bits ( 2 ) 1 = pwmxh pin is enabled for pwmx output 0 = pwmxh pin is disabled, i/o pin becomes a general purpose i/o bit 3 unimplemented: read as ? 0 ? bit 2-0 pen3l:pen1l: pwmxl i/o enable bits ( 2 ) 1 = pwmxl pin is enabled for pwmx output 0 = pwmxl pin is disabled, i/o pin becomes a general purpose i/o note 1: the pwmxcon1 register is a write-protected register. refer to section 15.3 ?write-protected registers? for more information on the unlock sequence. 2: the reset status for these bits depends on the setting of the pwmpin configuration bit (fpor<7>): ? if pwmpin = 1 (default), the pwm pins are controlled by the port register at reset, meaning they are initially programmed as inputs (i.e., tri-stated). ? if pwmpin = 0 , the pwm pins are controlled by the pwm module at reset and are therefore, initially programmed as output pins.
? 2011-2014 microchip technology inc. ds70000652f-page 189 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 15-6: pwmxcon2: pw mx control register 2 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? sevops<3:0> bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? iue osync udis bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as ? 0 ? bit 11-8 sevops<3:0>: pwmx special event trigger output postscale select bits 1111 = 1:16 postscale ? ? ? 0001 = 1:2 postscale 0000 = 1:1 postscale bit 7-3 unimplemented: read as ? 0 ? bit 2 iue: immediate update enable bit 1 = updates to the active pxdc registers are immediate 0 = updates to the active pxdc registers are synchronized to the pwmx time base bit 1 osync: output override synchronization bit 1 = output overrides via the pxovdcon register are synchronized to the pwmx time base 0 = output overrides via the pxovdcon register occur on the next t cy boundary bit 0 udis: pwmx update disable bit 1 = updates from duty cycle and period buffer registers are disabled 0 = updates from duty cycle and period buffer registers are enabled
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 190 ? 2011-2014 microchip technology inc. register 15-7: pxdtcon1: pwmx dead-time control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dtbps1 dtbps0 dtb5 dtb4 dtb3 dtb2 dtb1 dtb0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dtaps1 dtaps0 dta5 dta4 dta3 dta2 dta1 dta0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 dtbps<1:0>: dead-time unit b prescale select bits 11 = clock period for dead-time unit b is 8 t cy 10 = clock period for dead-time unit b is 4 t cy 01 = clock period for dead-time unit b is 2 t cy 00 = clock period for dead-time unit b is t cy bit 13-8 dtb<5:0>: unsigned 6-bit dead-time value for dead-time unit b bits bit 7-6 dtaps<1:0>: dead-time unit a prescale select bits 11 = clock period for dead-time unit a is 8 t cy 10 = clock period for dead-time unit a is 4 t cy 01 = clock period for dead-time unit a is 2 t cy 00 = clock period for dead-time unit a is t cy bit 5-0 dta<5:0>: unsigned 6-bit dead-time value for dead-time unit a bits
? 2011-2014 microchip technology inc. ds70000652f-page 191 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 15-8: pxdtcon2: pwmx dead-time control register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dts3a dts3i dts2a dts2i dts1a dts1i bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5 dts3a: dead-time select for pwm3 signal going active bit 1 = dead time provided from unit b 0 = dead time provided from unit a bit 4 dts3i: dead-time select for pwm3 signal going inactive bit 1 = dead time provided from unit b 0 = dead time provided from unit a bit 3 dts2a: dead-time select for pwm2 signal going active bit 1 = dead time provided from unit b 0 = dead time provided from unit a bit 2 dts2i: dead-time select for pwm2 signal going inactive bit 1 = dead time provided from unit b 0 = dead time provided from unit a bit 1 dts1a: dead-time select for pwm1 signal going active bit 1 = dead time provided from unit b 0 = dead time provided from unit a bit 0 dts1i: dead-time select for pwm1 signal going inactive bit 1 = dead time provided from unit b 0 = dead time provided from unit a
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 192 ? 2011-2014 microchip technology inc. register 15-9: pxfltacon: pwmx fault a control register ( 1 , 2 , 3 , 4 ) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? faov3h faov3l faov2h faov2l faov1h faov1l bit 15 bit 8 r/w-0 u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 fltam ? ? ? ? faen3 faen2 faen1 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 faov<3:1>h:faov<3:1>l: fault input a pwmx override value bits 1 = the pwmx output pin is driven active on an external fault input event 0 = the pwmx output pin is driven inactive on an external fault input event bit 7 fltam: fault a mode bit 1 = the fault a input pin functions in the cycle-by-cycle mode 0 = the fault a input pin latches all control pins to the programmed states in pxfltacon<13:8> bit 6-3 unimplemented: read as ? 0 ? bit 2 faen3: fault input a enable bit 1 = pwmxh3/pwmxl3 pin pair is controlled by fault input a 0 = pwmxh3/pwmxl3 pin pair is not controlled by fault input a bit 1 faen2: fault input a enable bit 1 = pwmxh2/pwmxl2 pin pair is controlled by fault input a 0 = pwmxh2/pwmxl2 pin pair is not controlled by fault input a bit 0 faen1: fault input a enable bit 1 = pwmxh1/pwmxl1 pin pair is controlled by fault input a 0 = pwmxh1/pwmxl1 pin pair is not controlled by fault input a note 1: comparator outputs are not internally connected to the pwm fault control logic. if using the comparator modules for fault generation, the user must externally connect the desired comparator output pin to the dedicated flta1 or fltb1 input pin. 2: refer to table 15-1 for flta1 implementation details. 3: the pxfltacon register is a write-protected register. refer to section 15.3 ?write-protected registers? for more information on the unlock sequence. 4: during any reset event, flta1 is enabled by default and must be cleared as described in section 15.2 ?pwm faults? .
? 2011-2014 microchip technology inc. ds70000652f-page 193 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 15-10: pxfltbcon: pwmx fault b control register ( 1 , 2 , 3 , 4 ) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? fbov3h fbov3l fbov2h fbov2l fbov1h fbov1l bit 15 bit 8 r/w-0 u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 fltbm ? ? ? ? fben3 fben2 fben1 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 fbov<3:1>h:fbov<3:1>l: fault input b pwmx override value bits 1 = the pwmx output pin is driven active on an external fault input event 0 = the pwmx output pin is driven inactive on an external fault input event bit 7 fltbm: fault b mode bit 1 = the fault b input pin functions in the cycle-by-cycle mode 0 = the fault b input pin latches all control pins to the programmed states in pxfltbcon<13:8> bit 6-3 unimplemented: read as ? 0 ? bit 2 fben3: fault input b enable bit 1 = pwmxh3/pwmxl3 pin pair is controlled by fault input b 0 = pwmxh3/pwmxl3 pin pair is not controlled by fault input b bit 1 fben2: fault input b enable bit 1 = pwmxh2/pwmxl2 pin pair is controlled by fault input b 0 = pwmxh2/pwmxl2 pin pair is not controlled by fault input b bit 0 fben1: fault input b enable bit 1 = pwmxh1/pwmxl1 pin pair is controlled by fault input b 0 = pwmxh1/pwmxl1 pin pair is not controlled by fault input b note 1: comparator outputs are not internally connected to the pwm fault control logic. if using the comparator modules for fault generation, the user must externally connect the desired comparator output pin to the dedicated flta1 or fltb1 input pin. 2: refer to table 15-1 for fltb1 implementation details. 3: the pxfltacon register is a write-protected register. refer to section 15.3 ?write-protected registers? for more information on the unlock sequence. 4: during any reset event, fltb1 is enabled by default and must be cleared as described in section 15.2 ?pwm faults? .
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 194 ? 2011-2014 microchip technology inc. register 15-11: pxovdcon: pwmx override control register u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? povd3h povd3l povd2h povd2l povd1h povd1l bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? pout3h pout3l pout2h pout2l pout1h pout1l bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 povd<3:1>h:povd<3:1>l: pwmx output override bits 1 = output on pwmx i/o pin is controlled by the pwmx generator 0 = output on pwmx i/o pin is controlled by the value in the corresponding poutxh:poutxl bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 pout<3:1>h:pout<3:1>l: pwm manual output bits 1 = pwmx i/o pin is driven active when the corresponding povdxh:povdxl bits are cleared 0 = pwmx i/o pin is driven inactive when the corresponding povdxh:povdxl bits are cleared
? 2011-2014 microchip technology inc. ds70000652f-page 195 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 15-12: pxdc1: pwmx duty cycle 1 register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdc1<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdc1<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 pdc1<15:0>: pwmx duty cycle 1 value bits register 15-13: pxdc2: pwmx duty cycle 2 register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdc2<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdc2<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 pdc2<15:0>: pwmx duty cycle 2 value bits register 15-14: pxdc3: pwmx duty cycle 3 register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdc3<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdc3<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 pdc3<15:0>: pwmx duty cycle 3 value bits
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 196 ? 2011-2014 microchip technology inc. register 15-15: pwmxkey: pwmx unlock register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pwmkey<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pwmkey<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 pwmkey<15:0>: pwmx unlock bits if the pwmlock configuration bit is asserted (pwmlock = 1 ), the pwmxcon1, pxfltacon and pxfltbcon registers are writable only after the proper sequence is written to the pwmxkey register. if the pwmlock configuration bit is deasserted (pwmlock = 0 ), the pwmxcon1, pxfltacon and pxfltbcon registers are writable at all times. refer to ?motor control pwm? (ds70187) in the ? dspic33/ pic24 family reference manual ? for details on the unlock sequence.
? 2011-2014 microchip technology inc. ds70000652f-page 197 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 16.0 serial peripheral interface (spi) the serial peripheral interface (spi) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices can be serial eeproms, shift regis- ters, display drivers, analog-to-digital converters, etc. the spi module is compatible with spi and siop from motorola ? . each spi module consists of a 16-bit shift register, spixsr (where x = 1 or 2), used for shifting data in and out, and a buffer register, spixbuf. a control register, spixcon, configures the module. additionally, a status register, spixstat, indicates status conditions. the serial interface consists of four pins: ? sdix (serial data input) ? sdox (serial data output) ? sckx (shift clock input or output) ? ssx (active-low slave select). in master mode operation, sckx is a clock output. in slave mode, it is a clock input. figure 16-1: spix mo dule block diagram note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to ?serial peripheral inter- face (spi)? (ds70206) in the ?dspic33/ pic24 family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. internal data bus sdix sdox ssx sckx spixsr bit 0 shift control edge select f cy primary 1:1/4/16/64 enable prescaler spixbuf transfer transfer write spixbuf read spixbuf 16 spixcon1<1:0> spixcon1<4:2> master clock clock control secondary prescaler 1:1 to 1:8 spixrxb spixtxb control sync
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 198 ? 2011-2014 microchip technology inc. 16.1 spi helpful tips 1. in frame mode, if there is a possibility that the master may not be initialized before the slave: a) if frmpol (spixcon2<13>) = 1 , use a pull-down resistor on ssx . b) if frmpol = 0 , use a pull-up resistor on ssx . 2. in non-framed 3-wire mode (i.e., not using ssx from a master): a) if ckp (spixcon1<6>) = 1 , always place a pull-up resistor on ssx . b) if ckp = 0 , always place a pull-down resistor on ssx . 3. frmen (spixcon2<15>) = 1 and ssen (spixcon1<7>) = 1 are exclusive and invalid. in frame mode, sckx is continuous and the frame sync pulse is active on the ssx pin, which indicates the start of a data frame. 4. in master mode only, set the smp bit (spixcon1<9>) to a ? 1 ? for the fastest spi data rate possible. the smp bit can only be set at the same time or after the msten bit (spixcon1<5>) is set. 5. to avoid invalid slave read data to the master, the user?s master software must ensure enough time for slave software to fill its write buffer before the user application initiates a master write/read cycle. it is always advisable to pre- load the spixbuf transmit register in advance of the next master transaction cycle. spixbuf is transferred to the spix shift register and is empty once the data transmission begins. 6. the spi related pins (sdi1, sdo1, sck1) are located at fixed positions in the dspic33fj16(gp/ mc)10x devices. the same pins are remappable in the dspic33fj32(gp/mc)10x devices. 16.2 spi resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 16.2.1 key resources ? ?serial peripheral interface (spi)? (ds70206) in the ? dspic33/pic24 family reference manual ?. ? code samples ? application notes ? software libraries ? webinars ? all related ? dspic33/pic24 family reference manual ? sections ? development tools note: this insures that the first frame transmission after initialization is not shifted or corrupted. note: this will insure that during power-up and initialization, the master/slave will not lose sync due to an errant sck transition that would cause the slave to accumulate data shift errors for both transmit and receive, appearing as corrupted data. note: not all third-party devices support frame mode timing. refer to the spi electrical characteristics for details. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554109
? 2011-2014 microchip technology inc. ds70000652f-page 199 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 16.3 spi control registers register 16-1: spixstat: spix status and control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 spien ? spisidl ? ? ? ? ? bit 15 bit 8 u-0 r/c-0 u-0 u-0 u-0 u-0 r-0 r-0 ? spirov ? ? ? ? spitbf spirbf bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 spien: spix enable bit 1 = enables module and configures sckx, sdox, sdix and ssx as serial port pins 0 = disables module bit 14 unimplemented: read as ? 0 ? bit 13 spisidl: spix stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 spirov: spix receive overflow flag bit 1 = a new byte/word is completely received and discarded; the user software has not read the previous data in the spixbuf register 0 = no overflow has occurred. bit 5-2 unimplemented: read as ? 0 ? bit 1 spitbf: spix transmit buffer full status bit 1 = transmit has not yet started, spixtxb is full 0 = transmit has started, spixtxb is empty automatically set in hardware when the cpu writes the spixbuf location, loading spixtxb. automatically cleared in hardware when the spix module transfers data from spixtxb to spixsr. bit 0 spirbf: spix receive buffer full status bit 1 = receive complete, spixrxb is full 0 = receive is not complete, spixrxb is empty automatically set in hardware when spix transfers data from spixsr to spixrxb. automatically cleared in hardware when the core reads the spixbuf location, reading spixrxb.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 200 ? 2011-2014 microchip technology inc. register 16-2: spi x con1: spix control register 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dissck dissdo mode16 smp cke ( 1 ) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssen ( 2 ) ckp msten spre2 ( 3 ) spre1 ( 3 ) spre0 ( 3 ) ppre1 ( 3 ) ppre0 ( 3 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 dissck: disable sckx pin bit (spi master modes only) 1 = internal spi clock is disabled, pin functions as i/o 0 = internal spi clock is enabled bit 11 dissdo: disable sdox pin bit 1 = sdox pin is not used by the module; pin functions as i/o 0 = sdox pin is controlled by the module bit 10 mode16: word/byte communication select bit 1 = communication is word-wide (16 bits) 0 = communication is byte-wide (8 bits) bit 9 smp: spix data input sample phase bit master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time slave mode: smp must be cleared when spix is used in slave mode. bit 8 cke: clock edge select bit ( 1 ) 1 = serial output data changes on transition from active clock state to idle clock state (see bit 6) 0 = serial output data changes on transition from idle clock state to active clock state (see bit 6) bit 7 ssen: spix slave select enable bit (slave mode) ( 2 ) 1 = ssx pin is used for slave mode 0 = ssx pin is not used by the module, pin is controlled by port function bit 6 ckp: clock polarity select bit 1 = idle state for clock is a high level; active state is a low level 0 = idle state for clock is a low level; active state is a high level bit 5 msten: master mode enable bit 1 = master mode 0 = slave mode note 1: the cke bit is not used in the framed spi modes. program this bit to ? 0 ? for the framed spi modes (frmen = 1 ). 2: this bit must be cleared when frmen = 1 . 3: do not set both primary and secondary prescalers to a value of 1:1.
? 2011-2014 microchip technology inc. ds70000652f-page 201 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 bit 4-2 spre<2:0>: secondary prescale bits (master mode) ( 3 ) 111 = secondary prescale 1:1 110 = secondary prescale 2:1 . . . 000 = secondary prescale 8:1 bit 1-0 ppre<1:0>: primary prescale bits (master mode) ( 3 ) 11 = primary prescale 1:1 10 = primary prescale 4:1 01 = primary prescale 16:1 00 = primary prescale 64:1 register 16-2: spi x con1: spix control register 1 (continued) note 1: the cke bit is not used in the framed spi modes. program this bit to ? 0 ? for the framed spi modes (frmen = 1 ). 2: this bit must be cleared when frmen = 1 . 3: do not set both primary and secondary prescalers to a value of 1:1.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 202 ? 2011-2014 microchip technology inc. register 16-3: spixcon2: spix control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 frmen spifsd frmpol ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 ? ? ? ? ? ? frmdly ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 frmen: framed spix support bit 1 = framed spix support is enabled (ssx pin is used as frame sync pulse input/output) 0 = framed spix support is disabled bit 14 spifsd: frame sync pulse direction control bit 1 = frame sync pulse input (slave) 0 = frame sync pulse output (master) bit 13 frmpol: frame sync pulse polarity bit 1 = frame sync pulse is active-high 0 = frame sync pulse is active-low bit 12-2 unimplemented: read as ? 0 ? bit 1 frmdly: frame sync pulse edge select bit 1 = frame sync pulse coincides with first bit clock 0 = frame sync pulse precedes first bit clock bit 0 unimplemented: this bit must not be set to ? 1 ? by the user application
? 2011-2014 microchip technology inc. ds70000652f-page 203 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 17.0 inter-integrated circuit? (i 2 c?) the inter-integrated circuit? (i 2 c?) module provides complete hardware support for both slave and multi- master modes of the i 2 c serial communication standard, with a 16-bit interface. the i 2 c module has a 2-pin interface: ? the sclx pin is clock ? the sdax pin is data the i 2 c module offers the following key features: ?i 2 c interface supporting both master and slave modes of operation ?i 2 c slave mode supports 7-bit and 10-bit addresses ?i 2 c master mode supports 7-bit and 10-bit addresses ?i 2 c port allows bidirectional transfers between master and slaves ? serial clock synchronization for i 2 c port can be used as a handshake mechanism to suspend and resume serial transfer (sclrel control) ?i 2 c supports multi-master operation, detects bus collision and arbitrates accordingly 17.1 operating modes the hardware fully implements all the master and slave functions of the i 2 c standard and fast mode specifications, as well as 7-bit and 10-bit addressing. the i 2 c module can operate either as a slave or a master on an i 2 c bus. the following types of i 2 c operation are supported: ?i 2 c slave operation with 7-bit addressing ?i 2 c slave operation with 10-bit addressing ?i 2 c master operation with 7-bit or 10-bit addressing for details about the communication sequence in each of these modes, refer to the microchip web site ( www.microchip.com ) for the latest ?dspic33/pic24 family reference manual? sections. 17.2 i 2 c registers i2cxcon and i2cxstat are control and status registers, respectively. the i2cxcon register is readable and writable. the lower six bits of i2cxstat are read-only. the remaining bits of the i2cxstat are read/write. ? i2cxrsr is the shift register used for shifting data ? i2cxrcv is the receive buffer and the register to which data bytes are written or from which data bytes are read ? i2cxtrn is the transmit register to which bytes are written during a transmit operation ? i2cxadd register holds the slave address ? add10 status bit indicates 10-bit addressing mode ? i2cxbrg acts as the baud rate generator (brg) reload value in receive operations, i2cxrsr and i2cxrcv together form a double-buffered receiver. when i2cxrsr receives a complete byte, it is transferred to i2cxrcv and an interrupt pulse is generated. note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to com- plement the information in this data sheet, refer to ?inter-integrated circuit? (i 2 c?)? (ds70195) in the ?dspic33/ pic24 family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 204 ? 2011-2014 microchip technology inc. figure 17-1: i 2 c? block diagram ( x = 1) internal data bus sclx sdax shift match detect i2cxadd clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control t cy /2 acknowledge generation i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxrcv collision detect start and stop bit generation start and stop bit detect i2cxmsk
? 2011-2014 microchip technology inc. ds70000652f-page 205 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 17.3 i 2 c control registers register 17-1: i2cxcon: i2cx control register r/w-0 u-0 r/w-0 r/w-1, hc r/w-0 r/w-0 r/w-0 r/w-0 i2cen ? i2csidl sclrel ipmien a10m disslw smen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc gcen stren ackdt acken rcen pen rsen sen bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 i2cen: i2cx enable bit 1 = enables the i2cx module, and configures the sdax and sclx pins as serial port pins 0 = disables the i2cx module; all i 2 c? pins are controlled by port functions bit 14 unimplemented: read as ? 0 ? bit 13 i2csidl: i2cx stop in idle mode bit 1 = discontinues module operation when device enters an idle mode 0 = continues module operation in idle mode bit 12 sclrel: sclx release control bit (when operating as i 2 c slave) 1 = releases sclx clock 0 = holds sclx clock low (clock stretch) if stren = 1 : bit is r/w (i.e., software can write ? 0 ? to initiate stretch and write ? 1 ? to release clock). hardware clears at beginning of every slave data byte transmission. hardware clears at end of every slave address byte reception. hardware clears at every slave data byte reception. if stren = 0 : bit is r/s (i.e., software can only write ? 1 ? to release clock). hardware clears at beginning of every slave data byte transmission. hardware clears at end of every slave address byte reception. bit 11 ipmien: intelligent peripheral management interface (ipmi) enable bit 1 = ipmi mode is enabled; all addresses are acknowledged 0 = ipmi mode is disabled bit 10 a10m: i2cx 10-bit slave address bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control is disabled 0 = slew rate control is enabled bit 8 smen: smbus input levels bit 1 = enables i/o pin thresholds compliant with smbus specification 0 = disables smbus input thresholds bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enables interrupt when a general call address is received in the i2cxrsr (module is enabled for reception) 0 = general call address is disabled
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 206 ? 2011-2014 microchip technology inc. bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with the sclrel bit. 1 = enables software or receives clock stretching 0 = disables software or receives clock stretching bit 5 ackdt: acknowledge data bit (when operating as i 2 c master, applicable during master receive) value that will be transmitted when the software initiates an acknowledge sequence. 1 = sends nack during acknowledge 0 = sends ack during acknowledge bit 4 acken: acknowledge sequence enable bit (when operating as i 2 c master, applicable during master receive) 1 = initiates acknowledge sequence on sdax and sclx pins and transmits ackdt data bit; hardware clears at end of master acknowledge sequence 0 = acknowledge sequence is not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c; hardware clears at end of eighth bit of the master receive data byte 0 = receive sequence is not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiates stop condition on sdax and sclx pins; hardware clears at end of the master stop sequence 0 = stop condition not in progress bit 1 rsen: repeated start condition enable bit (when operating as i 2 c master) 1 = initiates repeated start condition on sdax and sclx pins; hardware clears at end of the master repeated start sequence 0 = repeated start condition is not in progress bit 0 sen: start condition enable bit (when operating as i 2 c master) 1 = initiates start condition on sdax and sclx pins; hardware clears at end of master start sequence 0 = start condition is not in progress register 17-1: i2cxcon: i2cx control register (continued)
? 2011-2014 microchip technology inc. ds70000652f-page 207 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 17-2: i2cxstat: i2cx status register r-0, hsc r-0, hsc u-0 u-0 u-0 r/c-0, hs r-0, hsc r-0, hsc ackstat trstat ? ? ? bcl gcstat add10 bit 15 bit 8 r/c-0, hs r/c-0, hs r-0, hsc r/c-0, hsc r/c-0, hsc r-0, hsc r-0, hsc r-0, hsc iwcol i2cov d_a p s r_w rbf tbf bit 7 bit 0 legend: c = clearable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown hs = hardware settable bit bit 15 ackstat: acknowledge status bit (when operating as i 2 c? master, applicable to master transmit operation) 1 = nack received from slave 0 = ack received from slave hardware sets or clears at end of slave acknowledge. bit 14 trstat: transmit status bit (when operating as i 2 c master, applicable to master transmit operation) 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress hardware sets at beginning of master transmission. hardware clears at end of slave acknowledge. bit 13-11 unimplemented: read as ? 0 ? bit 10 bcl: master bus collision detect bit 1 = a bus collision has been detected during a master operation 0 = no collision hardware sets at detection of bus collision. bit 9 gcstat: general call status bit 1 = general call address was received 0 = general call address was not received hardware sets when address matches general call address. hardware clears at stop detection. bit 8 add10: 10-bit address status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched hardware sets at match of 2nd byte of matched 10-bit address. hardware clears at stop detection. bit 7 iwcol: write collision detect bit 1 = an attempt to write to the i2cxtrn register failed because the i 2 c module is busy 0 = no collision hardware sets at occurrence of a write to i2cxtrn while busy (cleared by software). bit 6 i2cov: receive overflow flag bit 1 = a byte was received while the i2cxrcv register is still holding the previous byte 0 = no overflow hardware sets at attempt to transfer i2 cxrsr to i2cxrcv (cleared by software). bit 5 d_a: data/address bit (when operating as i 2 c slave) 1 = indicates that the last byte received was data 0 = indicates that the last byte received was a device address hardware clears at device address match. hardware sets by reception of a slave byte.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 208 ? 2011-2014 microchip technology inc. bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last hardware sets or clears when start, repeated start or stop is detected. bit 3 s: start bit 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last hardware sets or clears when start, repeated start or stop is detected. bit 2 r_w: read/write information bit (when operating as i 2 c slave) 1 = read ? indicates data transfer is output from slave 0 = write ? indicates data transfer is input to slave hardware sets or clears after reception of an i 2 c device address byte. bit 1 rbf: receive buffer full status bit 1 = receive is complete, i2cxrcv is full 0 = receive is not complete, i2cxrcv is empty hardware sets when i2cxrcv is written with received byte. hardware clears when software reads i2cxrcv. bit 0 tbf: transmit buffer full status bit 1 = transmit in progress, i2cxtrn is full 0 = transmit complete, i2cxtrn is empty hardware sets when software writes to i2cxtrn. hardware clears at completion of data transmission. register 17-2: i2cxstat: i2cx status register (continued)
? 2011-2014 microchip technology inc. ds70000652f-page 209 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 17-3: i2cxmsk: i2cx sl ave mode address mask register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? amsk<9:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 amsk<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as ? 0 ? bit 9-0 amsk<9:0>: mask for address bit x select bits 1 = enables masking for bit x of incoming message address; bit match not required in this position 0 = disables masking for bit x; bit match required in this position
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 210 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 211 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 18.0 universal asynchronous receiver transmitter (uart) the universal asynchronous receiver transmitter (uart) module is one of the serial i/o modules available in the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 device family. the uart is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, lin/j2602, rs-232 and rs-485 interfaces. the module also supports a hardware flow control option with the uxcts and uxrts pins, and also includes an irda ? encoder and decoder. the primary features of the uart module are: ? full-duplex, 8-bit or 9-bit data transmission through the uxtx and uxrx pins ? even, odd or no parity options (for 8-bit data) ? one or two stop bits ? hardware flow control option with uxcts and uxrts pins ? fully integrated baud rate generator with 16-bit prescaler ? baud rates ranging from 1 mbps to 6 bps at 16x mode at 16 mips ? baud rates ranging from 4 mbps to 24.4 bps at 4x mode at 16 mips ? 4-deep first-in first-out (fifo) transmit data buffer ? 4-deep fifo receive data buffer ? parity, framing and buffer overrun error detection ? support for 9-bit mode with address detect (9th bit = 1 ) ? transmit and receive interrupts ? a separate interrupt for all uart error conditions ? loopback mode for diagnostic support ? support for sync and break characters ? support for automatic baud rate detection ?irda ? encoder and decoder logic ? 16x baud clock output for irda ? support a simplified block diagram of the uart module is shown in figure 18-1 . the uart module consists of these key hardware elements: ? baud rate generator ? asynchronous transmitter ? asynchronous receiver figure 18-1: uartx simp lified block diagram note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a comprehensive reference source. to com- plement the information in this data sheet, refer to ?uart? (ds70188) in the ?dspic33/pic24 family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. uxrx hardware flow control uartx receiver uartx transmitter uxtx baud rate generator uxrts / bclk uxcts irda ?
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 212 ? 2011-2014 microchip technology inc. 18.1 uart helpful tips 1. in multi-node, direct connect uart networks, uart receive inputs react to the complementary logic level defined by the urxinv bit (uxmode<4>), which defines the idle state, the default of which is logic high (i.e., urxinv = 0 ). because remote devices do not initialize at the same time, it is likely that one of the devices, because the rx line is floating, will trigger a start bit detection and will cause the first byte received after the device has been initialized to be invalid. to avoid this situation, the user should use a pull-up or pull-down resistor on the rx pin depending on the value of the urxinv bit. a) if urxinv = 0 , use a pull-up resistor on the rx pin. b) if urxinv = 1 , use a pull-down resistor on the rx pin. 2. the first character received on a wake-up from sleep mode caused by activity on the uxrx pin of the uart module will be invalid. in sleep mode, peripheral clocks are disabled. by the time the oscillator system has restarted and stabilized from sleep mode, the baud rate bit sampling clock, relative to the incoming uxrx bit timing, is no longer synchronized, resulting in the first character being invalid; this is to be expected. 18.2 uart resources many useful resources are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 18.2.1 key resources ? ?uart? (ds70188) in the ?dspic33/pic24 family reference manual? ? code samples ? application notes ? software libraries ? webinars ? all related ?dspic33/pic24 family reference manual? sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554109
? 2011-2014 microchip technology inc. ds70000652f-page 213 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 18.3 uart control registers register 18-1: uxmode: uart x mode register r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 uarten ( 1 ) ? usidl iren ( 2 ) rtsmd ?uen1uen0 bit 15 bit 8 r/w-0, hc r/w-0 r/w-0, hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud urxinv brgh pdsel1 pdsel0 stsel bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 uarten: uartx enable bit ( 1 ) 1 = uartx is enabled; all uartx pins are controlled by uartx as defined by the uen<1:0> bits 0 = uartx is disabled; all uartx pins are controlled by port latches; uartx power consumption is minimal bit 14 unimplemented: read as ? 0 ? bit 13 usidl: uartx stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12 iren: irda ? encoder and decoder enable bit ( 2 ) 1 = irda encoder and decoder are enabled 0 = irda encoder and decoder are disabled bit 11 rtsmd: uartx mode selection for uxrts pin bit 1 =uxrts pin is in simplex mode 0 =uxrts pin is in flow control mode bit 10 unimplemented: read as ? 0 ? bit 9-8 uen<1:0>: uartx pin enable bits 11 = uxtx, uxrx and bclk pins are enabled and used; uxcts pin is controlled by port latches 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin is controlled by port latches 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /bclk pins are controlled by port latches bit 7 wake: wake-up on start bit detect during sleep mode enable bit 1 = uartx will continue to sample the uxrx pin; interrupt is generated on falling edge, bit is cleared in hardware on following rising edge 0 = no wake-up is enabled bit 6 lpback: uartx loopback mode select bit 1 = enables loopback mode 0 = loopback mode is disabled bit 5 abaud: auto-baud enable bit 1 = enables baud rate measurement on the next character ? requires reception of a sync field (55h) before other data; cleared in hardware upon completion 0 = baud rate measurement is disabled or completed note 1: refer to ?uart? (ds70188) in the ?dspic33/pic24 family reference manual? for information on enabling the uart module for receive or transmit operation. 2: this feature is available for 16x brg mode (brgh = 0 ) only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 214 ? 2011-2014 microchip technology inc. bit 4 urxinv: uartx receive polarity inversion bit 1 = uxrx idle state is ? 0 ? 0 = uxrx idle state is ? 1 ? bit 3 brgh: high baud rate enable bit 1 = brg generates 4 clocks per bit period (4x baud clock, high-speed mode) 0 = brg generates 16 clocks per bit period (16x baud clock, standard mode) bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop bit selection bit 1 = two stop bits 0 = one stop bit register 18-1: uxmode: uart x mode register (continued) note 1: refer to ?uart? (ds70188) in the ?dspic33/pic24 family reference manual? for information on enabling the uart module for receive or transmit operation. 2: this feature is available for 16x brg mode (brgh = 0 ) only.
? 2011-2014 microchip technology inc. ds70000652f-page 215 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 18-2: u x sta: uart x status and control register r/w-0 r/w-0 r/w-0 u-0 r/w-0, hc r/w-0 r-0 r-1 utxisel1 utxinv utxisel0 ? utxbrk utxen ( 1 ) utxbf trmt bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-1 r-0 r-0 r/c-0 r-0 urxisel1 urxisel0 adden ridle perr ferr oerr urxda bit 7 bit 0 legend: c = clearable bit hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15,13 utxisel<1:0>: uartx transmission interrupt mode selection bits 11 = reserved; do not use 10 = interrupt when a character is transferred to the transmit shift register (tsr) and as a result, the transmit buffer becomes empty 01 = interrupt when the last character is shifted out of the transmit shift register; all transmit operations are completed 00 = interrupt when a character is transferred to the transmit shift register (this implies there is at least one character open in the transmit buffer) bit 14 utxinv: uartx transmit polarity inversion bit if iren = 0 : 1 = uxtx idle state is ? 0 ? 0 = uxtx idle state is ? 1 ? if iren = 1 : 1 = irda encoded, uxtx idle state is ? 1 ? 0 = irda encoded, uxtx idle state is ? 0 ? bit 12 unimplemented: read as ? 0 ? bit 11 utxbrk: uartx transmit break bit 1 = sends sync break on next transmission ? start bit, followed by twelve ? 0 ? bits, followed by stop bit; cleared by hardware upon completion 0 = sync break transmission is disabled or completed bit 10 utxen: uartx transmit enable bit ( 1 ) 1 = transmit is enabled, uxtx pin is controlled by uartx 0 = transmit is disabled, any pending transmission is aborted and the buffer is reset; uxtx pin is controlled by port bit 9 utxbf: uartx transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at least one more character can be written bit 8 trmt: transmit shift register empty bit (read-only) 1 = transmit shift register is empty and transmit bu ffer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmission is in progress or queued bit 7-6 urxisel<1:0>: uartx receive interrupt mode selection bits 11 = interrupt is set on uxrsr transfer, making the receive buffer full (i.e., has 4 data characters) 10 = interrupt is set on uxrsr transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = interrupt is set when any character is received and transferred from the uxrsr to the receive buffer; receive buffer has one or more characters note 1: refer to ?uart? (ds70188) in the ?dspic33/pic24 family reference manual? for information on enabling the uart module for transmit operation.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 216 ? 2011-2014 microchip technology inc. bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = address detect mode is disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = receiver is active bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current character (character at the top of the receive fifo) 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character (character at the top of the receive fifo) 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit (read-only/clear only) 1 = receive buffer has overflowed 0 = receive buffer has not overflowed; clearing a previously set oerr bit ( 1 ? 0 transition) will reset the receiver buffer and the uxrsr to the empty state bit 0 urxda: uartx receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 18-2: u x sta: uart x status and control register (continued) note 1: refer to ?uart? (ds70188) in the ?dspic33/pic24 family reference manual? for information on enabling the uart module for transmit operation.
? 2011-2014 microchip technology inc. ds70000652f-page 217 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 19.0 10-bit analog-to-digital converter (adc) the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices have up to 14 adc module input channels. 19.1 key features the 10-bit adc configuration has the following key features: ? successive approximation (sar) conversion ? conversion speeds of up to 1.1 msps ? up to 14 analog input pins ? four sample-and-hold (s&h) circuits for simultaneous sampling of up to four analog input pins ? automatic channel scan mode ? selectable conversion trigger source ? selectable buffer fill modes ? four result alignment options (signed/unsigned, fractional/integer) ? operation during cpu sleep and idle modes ? 16-word conversion result buffer depending on the particular device pinout, the adc can have up to 14 analog input pins. block diagrams of the adc module are shown in figure 19-1 through figure 19-3 . 19.2 adc initialization to configure the adc module: 1. select port pins as analog inputs (ad1pcfgl<15:0>). 2. select the analog conversion clock to match the desired data rate with the processor clock (adxcon3<7:0>). 3. determine how many sample-and-hold channels will be used (adxcon2<9:8>). 4. select the appropriate sample and conver- sion sequence (adxcon1<7:5> and adxcon3<12:8>). 5. select the way conversion results are presented in the buffer (adxcon1<9:8>). 6. turn on the adc module (adxcon1<15>). 7. configure the adc interrupt (if required): a) clear the adxif bit. b) select the adc interrupt priority. note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family devices. it is not intended to be a compre- hensive reference source. to complement the information in this data sheet, refer to ?analog-to-digital converter (adc)? (ds70183) in the ?dspic33/ pic24 family reference manual?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 218 ? 2011-2014 microchip technology inc. figure 19-1: adc1 block diagram fo r dspic33fjxx(gp/mc)101 devices s&h0 s&h1 adc1buf0 adc1buf1 adc1buf2 adc1buff adc1bufe an0-an3 an10 (3) an1 v refl ch0sb<4:0> ch0na ch0nb + - an0 an3 ch123sa v refl ch123sb ch123na ch123nb + - s&h2 an1 ch123sa v refl ch123sb ch123na ch123nb + - s&h3 an2 ch123sa v refl ch123sb ch123na ch123nb + - ch1 ch0 ch2 ch3 ch0sa<4:0> channel scan cscna alternate input selection ctmu temp (1) note 1: internally connected to the ctmu module. 2: this selection is only used with ctmu capacitive and time measurement. 3: this pin is available in dspic33fj32(gp/mc)101 devices only. open (2) ctmui (1) av dd av ss vcfg<2:0> an9 (3) an10 (3) an9 (3) sar adc v refh v refl
? 2011-2014 microchip technology inc. ds70000652f-page 219 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 19-2: adc1 block di agram for dspic33fjxx(gp/mc)102 devices sar adc s&h0 s&h1 adc1buf0 adc1buf1 adc1buf2 adc1buff adc1bufe an0-an5 an10 (3) an1 v refl ch0sb<4:0> ch0na ch0nb + - an0 an3 ch123sa v refl ch123sb ch123na ch123nb + - s&h2 an1 an4 ch123sa v refl ch123sb ch123na ch123nb + - s&h3 an2 an5 ch123sa v refl ch123sb ch123na ch123nb + - ch1 ch0 ch2 ch3 ch0sa<4:0> channel scan cscna alternate input selection v refh v refl ctmu temp (1) note 1: internally connected to the ctmu module. 2: this selection is only used with ctmu capacitive and time measurement. 3: this pin is available in dspic33fj32(gp/mc)101 devices only. open (2) ctmui (1) an9 (3) an10 (3) an9 (3) av dd av ss vcfg<2:0>
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 220 ? 2011-2014 microchip technology inc. figure 19-3: adc1 block diagram for dspic33fj32(gp/mc)104 devices sar adc s&h0 s&h1 adc1buf0 adc1buf1 adc1buf2 adc1buff adc1bufe an0-an12 an15 an1 v refl ch0sb<4:0> ch0na ch0nb + - an0 an3 ch123sa v refl ch123sb ch123na ch123nb + - s&h2 an1 an4 ch123sa v refl ch123sb ch123na ch123nb + - s&h3 an2 an5 ch123sa v refl ch123sb ch123na ch123nb + - ch1 ch0 ch2 ch3 ch0sa<4:0> channel scan cscna alternate input selection v refh v refl ctmu temp (1) note 1: internally connected to the ctmu module. 2: this selection is only used with ctmu capacitive and time measurement. open (2) ctmui (1) an6 an10 an9 an7 an11 an8 av dd av ss vcfg<2:0>
? 2011-2014 microchip technology inc. ds70000652f-page 221 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 19-4: adc1 conversion clock period block diagram 19.3 adc helpful tips 1. the smpi<3:0> (ad1con2<5:2>) control bits: a) determine when the adc interrupt flag is set and an interrupt is generated if enabled. b) when the cscna bit (ad1con2<10>) is set to ? 1 ?, determine when the adc analog scan channel list, defined in the ad1cssl register, starts over from the beginning. 2. the adc has 16 result buffers. adc conversion results are stored sequentially in adc1buf0- adc1buff, regardless of which analog inputs are being used, subject to the smpi<3:0> bits (ad1con2<5:2>). there is no relationship between the anx input being measured and which adc buffer (adc1buf0-adc1buff) that the conversion results will be placed in. 3. the done bit (ad1con1<0>) is only cleared at the start of each conversion and is set at the completion of the conversion, but remains set indefinitely, even through the next sample phase until the next conversion begins. if application code is monitoring the done bit in any kind of software loop, the user must consider this behavior because the cpu code execution is faster than the adc. as a result, in manual sample mode, particularly where the user?s code is setting the samp bit (ad1con1<1>), the done bit should also be cleared by the user application just before setting the samp bit. 19.4 adc resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 19.4.1 key resources ? ?analog-to-digital converter (adc)? (ds70183) in the ?dspic33/pic24 family reference manual? ? code samples ? application notes ? software libraries ? webinars ? all related ?dspic33/pic24 family reference manual? sections ? development tools 1 0 adc1 internal rc clock (1) t osc (1) x 2 adc1 conversion clock multiplier 1, 2, 3, 4, 5,..., 64 ad1con3<15> t cy t ad 6 ad1con3<5:0> note 1: see the adc specifications in section 26.0 ?electrical characteristics? for the exact rc clock value. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http:// www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554109
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 222 ? 2011-2014 microchip technology inc. 19.5 adc control registers register 19-1: ad1con1: adc1 control register 1 r/w-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 adon ?adsidl ? ? ?form1form0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0, hc, hs r/c-0, hc, hs ssrc2 ssrc1 ssrc0 ? simsam asam samp done bit 7 bit 0 legend: c = clearable bit hs = hardware settable bit hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adon: adc1 operating mode bit 1 = adc1 module is operating 0 = adc1 is off bit 14 unimplemented: read as ? 0 ? bit 13 adsidl: adc1 stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12-10 unimplemented: read as ? 0 ? bit 9-8 form<1:0>: data output format bits 11 = signed fractional (d out = sddd dddd dd00 0000 , where s = .not.d<9> ) 10 = fractional (d out = dddd dddd dd00 0000 ) 01 = signed integer (d out = ssss sssd dddd dddd , where s = .not.d<9> ) 00 = integer (d out = 0000 00dd dddd dddd ) bit 7-5 ssrc<2:0>: sample clock source select bits 111 = internal counter ends sampling and starts conversion (auto-convert) 110 =ctmu 101 = reserved 100 = reserved 011 = motor control pwm interval ends sampling and starts conversion ( 1 ) 010 = gp timer3 compare ends sampling and starts conversion 001 = active transition on int0 pin ends sampling and starts conversion 000 = clearing samp bit ends sampling and starts conversion bit 4 unimplemented: read as ? 0 ? bit 3 simsam: simultaneous sample select bit (applicable only when chps<1:0> = 01 or 1x ) 1 = samples ch0, ch1, ch2, ch3 simultaneously (when chps<1:0> = 1x ) or samples ch0 and ch1 simultaneously (when chps<1:0> = 01 ) 0 = samples multiple channels individually in sequence bit 2 asam: adc1 sample auto-start bit 1 = sampling begins immediately after last conversion; samp bit is auto-set 0 = sampling begins when the samp bit is set note 1: this feature is available in dspic33fj(16/32)mc10x devices only.
? 2011-2014 microchip technology inc. ds70000652f-page 223 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 bit 1 samp: adc1 sample enable bit 1 = adc1 sample-and-hold amplifiers are sampling 0 = adc1 sample-and-hold amplifiers are holding if asam = 0 , software can write ? 1 ? to begin sampling; automatically set by hardware if asam = 1 . if ssrc<2:0> = 000 , software can write ? 0 ? to end sampling and start conversion. if ssrc<2:0> ?? 000 , automatically cleared by hardware to end sampling and start conversion. bit 0 done: adc1 conversion status bit 1 = adc1 conversion cycle is completed 0 = adc1 conversion has not started or is in progress automatically set by hardware when adc conversion is complete. software can write ? 0 ? to clear the done bit status (software not allowed to write ? 1 ?). clearing this bit will not affect any operation in progress. automatically cleared by hardware at start of a new conversion. register 19-1: ad1con1: adc1 control register 1 (continued) note 1: this feature is available in dspic33fj(16/32)mc10x devices only.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 224 ? 2011-2014 microchip technology inc. register 19-2: ad1con2: adc1 control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 vcfg2 vcfg1 vcfg0 ? ? cscna chps1 chps0 bit 15 bit 8 r-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufs ? smpi3 smpi2 smpi1 smpi0 bufm alts bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 vcfg<2:0>: converter voltage reference configuration bits bit 12-11 unimplemented: read as ? 0 ? bit 10 cscna: scan input selections for ch0+ during sample a bit 1 = scans inputs 0 = does not scan inputs bit 9-8 chps<1:0>: select channels utilized bits 1x = converts ch0, ch1, ch2 and ch3 01 = converts ch0 and ch1 00 = converts ch0 bit 7 bufs: buffer fill status bit (valid only when bufm = 1 ) 1 = adc1 is currently filling second half of buffer, user should access data in the first half 0 = adc1 is currently filling first half of buffer, user application should access data in the second half bit 6 unimplemented: read as ? 0 ? bit 5-2 smpi<3:0>: sample/convert sequences per interrupt selection bits 1111 = interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = interrupts at the completion of conversion for each 15th sample/convert sequence ? ? ? 0001 = interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = interrupts at the completion of conversion for each sample/convert sequence bit 1 bufm: buffer fill mode select bit 1 = starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt 0 = always starts filling buffer from the beginning bit 0 alts: alternate input sample mode select bit 1 = uses channel input selects for sample a on first sample and sample b on next sample 0 = always uses channel input selects for sample a adref+ adref- xxx av dd av ss
? 2011-2014 microchip technology inc. ds70000652f-page 225 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 19-3: ad1con3: adc1 control register 3 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adrc ? ? samc4 ( 1 ) samc3 ( 1 ) samc2 ( 1 ) samc1 ( 1 ) samc0 ( 1 ) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs7 ( 2 ) adcs6 ( 2 ) adcs5 ( 2 ) adcs4 ( 2 ) adcs3 ( 2 ) adcs2 ( 2 ) adcs1 ( 2 ) adcs0 ( 2 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adrc: adc1 conversion clock source bit 1 = adc1 internal rc clock 0 = clock derived from system clock bit 14-13 unimplemented: read as ? 0 ? bit 12-8 samc<4:0>: auto-sample time bits ( 1 ) 11111 = 31 t ad ? ? ? 00001 = 1 t ad 00000 = 0 t ad bit 7-0 adcs<7:0>: adc1 conversion clock select bits ( 2 ) 11111111 = reserved ? ? ? ? 01000000 = reserved 00111111 = t cy ? (adcs<7:0> + 1) = 64 ? t cy = t ad ? ? ? 00000010 = t cy ? (adcs<7:0> + 1) = 3 ? t cy = t ad 00000001 = t cy ? (adcs<7:0> + 1) = 2 ? t cy = t ad 00000000 = t cy ? (adcs<7:0> + 1) = 1 ? t cy = t ad note 1: this bit is only used if ssrc<2:0> (ad1con1<7:5>) = 1 . 2: this bit is not used if adrc (ad1con3<15>) = 1 .
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 226 ? 2011-2014 microchip technology inc. register 19-4: ad1chs123: adc1 input channel 1, 2, 3 select register u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? ch123nb1 ch123nb0 ch123sb bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? ch123na1 ch123na0 ch123sa bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-9 ch123nb<1:0>: channel 1, 2, 3 negative input select for sample b bits dspic33fj16(gp/mc)101/102 devices only: 11 = reserved 10 = reserved 0x = ch1, ch2, ch3 negative inputs are av ss dspic33fj32(gp/mc)101/102 devices only: 11 = ch1 negative input is an9, ch2 negative input is an10, ch3 negative input is not connected 10 = reserved 0x = ch1, ch2, ch3 negative inputs are av ss dspic33fj32(gp/mc)104 devices only: 11 = ch1 negative input is an9, ch2 negative input is an10, ch3 negative input is an11 10 = ch1 negative input is an6, ch2 negative input is an7, ch3 negative input is an8 0x = ch1, ch2, ch3 negative inputs are av ss bit 8 ch123sb: channel 1, 2, 3 positive input select for sample b bit dspic33fjxx(gp/mc)101 devices only: 1 = ch1 positive input is an3, ch2 and ch3 positive inputs are not connected 0 = ch1 positive input is an0, ch2 positive input is an1, ch3 positive input is an2 all other devices: 1 = ch1 positive input is an3, ch2 positive input is an4, ch3 positive input is an5 0 = ch1 positive input is an0, ch2 positive input is an1, ch3 positive input is an2 bit 7-3 unimplemented: read as ? 0 ? bit 2-1 ch123na<1:0>: channel 1, 2, 3 negative input select for sample a bits refer to bits<10-9> for the available settings. bit 0 ch123sa: channel 1, 2, 3 positive input select for sample a bit refer to bit 8 for the available settings.
? 2011-2014 microchip technology inc. ds70000652f-page 227 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 19-5: ad1chs0: adc1 input channel 0 select register r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0nb ? ? ch0sb4 ch0sb3 ch0sb2 ch0sb1 ch0sb0 bit 15 bit 8 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0na ? ? ch0sa4 ch0sa3 ch0sa2 ch0sa1 ch0sa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ch0nb: channel 0 negative input select for sample b bit 1 = channel 0 negative input is an1 0 = channel 0 negative input is av ss bit 14-13 unimplemented: read as ? 0 ? bit 12-8 ch0sb<4:0>: channel 0 positive input select for sample b bits 11111-10000 = reserved; do not use 01111 = channel 0 positive input is an15 ( 2 ) 01110 = no channels connected, all inputs are floating (used for ctmu) 01101 = channel 0 positive input is connected to ctmu temperature sensor 01100 = channel 0 positive input is an12 ( 2 ) 01011 = channel 0 positive input is an11 ( 2 ) 01010 = channel 0 positive input is an10 ( 3 ) 01001 = channel 0 positive input is an9 ( 3 ) 01000 = channel 0 positive input is an8 ( 2 ) 00111 = channel 0 positive input is an7 ( 2 ) 00110 = channel 0 positive input is an6 ( 2 ) 00101 = channel 0 positive input is an5 ( 1 ) 00100 = channel 0 positive input is an4 ( 1 ) 00011 = channel 0 positive input is an3 00010 = channel 0 positive input is an2 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 bit 7 ch0na: channel 0 negative input select for sample a bit 1 = channel 0 negative input is an1 0 = channel 0 negative input is av ss bit 6-5 unimplemented: read as ? 0 ? bit 4-0 ch0sa<4:0>: channel 0 positive input select for sample a bits refer to bits<12-8> for the available settings. note 1: this setting is available in all devices, excluding the dspic33fjxx(gp/mc)101, where it is reserved. 2: this setting is available in the dspic33fj32(gp/mc)104 devices only and is reserved in all other devices. 3: this setting is available in all devices, excluding the dspic33fj16(gp/mc)101/102, where it is reserved.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 228 ? 2011-2014 microchip technology inc. ,2 register 19-6: ad1cssl: adc1 input scan select register low ( 1 , 2 , 3 ) r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css15 ( 4 ) ? ?css<12:8> ( 4,6 ) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css<7:0> ( 4,5 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 css15: adc1 input scan selection bit ( 4 ) 1 = selects anx for input scan 0 = skips anx for input scan bit 14-13 unimplemented: read as ? 0 ? bit 12-0 css<12:0>: adc1 input scan selection bits ( 4 , 5 , 6 ) 1 = selects anx for input scan 0 = skips anx for input scan note 1: on devices without 14 analog inputs, all ad1cssl bits can be selected by the user application. however, inputs selected for scan without a corresponding input on the device converts v refl . 2: cssx = anx, where x = 0 through 12 and 15. 3: ctmu temperature sensor input cannot be scanned. 4: the css<15,12:11,8:6> bits are available in the dspic33fj32(gp/mc)104 devices only and are reserved in all other devices. 5: the css<5:4> bits are available on all devices, excluding the dspic33fjxx(gp/mc)101 devices, where they are reserved. 6: the css<10:9> bits are available on all devices, excluding the dspic33fj16(gp/mc)101/102 devices, where they are reserved.
? 2011-2014 microchip technology inc. ds70000652f-page 229 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 19-7: ad1pcfgl: adc1 po rt configuration register low ( 1 , 2 , 3 ) r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pcfg15 ( 4 , 5 ) ? ?pcfg<12:0> ( 4 , 5,7 ) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pcfg<7:0> ( 4 , 5,6 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 pcfg15: adc1 port configuration control bit ( 4 , 5 ) 1 = port pin is in digital mode, port read input is enabled, adc1 input multiplexer is connected to av ss 0 = port pin is in analog mode, port read input is disabled, adc1 samples pin voltage bit 14-13 unimplemented: read as ? 0 ? bit 12-0 pcfg<12:0>: adc1 port configuration control bits ( 4 , 5 , 6 , 7 ) 1 = port pin is in digital mode, port read input is enabled, adc1 input multiplexer is connected to av ss 0 = port pin is in analog mode, port read input is disabled, adc1 samples pin voltage note 1: on devices without 14 analog inputs, all pcfgx bits are r/w by user. however, pcfgx bits are ignored on ports without a corresponding input on the device. 2: pcfgx = anx, where x = 0 through 12 and 15. 3: the pcfgx bits have no effect if the adc module is disabled by setting the ad1md bit in the pmd1 register. when the bit is set, all port pins that have been multiplexed with anx will be in digital mode. 4: pins shared with analog functions (i.e., anx) are analog by default and therefore, must be set by the user to enable any digital function on that pin. reading any port pin with the analog function enabled will return a ? 0 ?, regardless of the signal input level. 5: the pcfg<15,12:11,8:6> bits are available in the dspic33fj32(gp/mc)104 devices only and are reserved in all other devices. 6: the pcfg<5:4> bits are available on all devices, excluding the dspic33fjxx(gp/mc)101 devices, where they are reserved. 7: the pcfg<10:9> bits are available on all devices, excluding the dspic33fj16(gp/mc)101/102 devices, where they are reserved.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 230 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 231 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 20.0 comparator module the comparator module provides three comparators that can be configured in different ways. as shown in figure 20-1 , individual comparator options are specified by the comparator module?s special function register (sfr) control bits. these options allow users to: ? select the edge for trigger and interrupt generation ? select low-power control ? configure the comparator voltage reference and band gap ? configure output blanking and masking the comparator operating mode is determined by the input selections (i.e., whether the input voltage is compared to a second input voltage) to an internal voltage reference. figure 20-1: comparator i/o operating modes note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 device families. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to ?comparator with blank- ing? (ds70647) in the ? dspic33/pic24 family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. c3 c1 blanking function digital filter c2 cv ref ( figure 20-3 )( figure 20-4 ) ? + v in - v in + ? + v in - v in + ? + v in - v in + bgsel<1:0> av dd av ss iv ref (1) c1inb c1inc c1ind mux c1ina intref mux c2inb c2inc c2ind c2ina intref cv refin mux c3inb c3inc c3ind mux c3ina intref cv refin cv refin c1out cpol interrupt logic evpol<1:0> coe cout blanking function digital filter ( figure 20-3 ) ( figure 20-4 ) c2out cpol interrupt logic evpol<1:0> coe cout digital filter ( figure 20-4 ) c3out cpol interrupt logic evpol<1:0> coe cout note 1: this reference voltage is generated in ternally on the device. refer to section 26.0 ?electrical characteristics? for the specified voltage range. mux mux function ( figure 20-3 ) blanking reference ( figure 20-2 ) comparator voltage
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 232 ? 2011-2014 microchip technology inc. figure 20-2: comparator volt age reference block diagram figure 20-3: user-programmable blanking function block diagram 8r r cvren av dd (1) 8r r r r r r r 16 steps cvrr cv ref cvr3 cvr2 cvr1 cvr0 cvrcon<3:0> av ss (1) cv rsrc cvroe (cvrcon<6>) cv refin vrefsel note 1: this pin is v dd and v ss on devices that have no av dd or av ss pins. 16-to-1 mux selsrca<3:0> selsrcb<3:0> selsrcc<3:0> and cmxmskcon mux a mai mbi mci comparator output to digital signals filter or blanking blanking blanking signals signals andi mask ?and-or? function hlms mux c blanking logic (cmxmskcon<15>) (cmxmsksrc<11:8) (cmxmsksrc<7:4) (cmxmsksrc<3:0>) mbi mci mai mbi mci mai mux b
? 2011-2014 microchip technology inc. ds70000652f-page 233 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 20-4: digital filter interconnect block diagram c x out cfltren digital filter timer2 f osc f cy cfsel<2:0> ?? cfdiv from blanking logic timer3 pwm special event trigger
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 234 ? 2011-2014 microchip technology inc. 20.1 comparator control registers register 20-1: cmstat: comparator status register r/w-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 cmsidl ? ? ? ? c3evt c2evt c1evt bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 ? ? ? ? ? c3out c2out c1out bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 cmsidl: comparator stop in idle mode bit 1 = discontinues operation of all comparators when device enters idle mode 0 = continues operation of all comparators in idle mode bit 14-11 unimplemented: read as ? 0 ? bit 10 c3evt: comparator 3 event status bit 1 = comparator event occurred 0 = comparator event did not occur bit 9 c2evt: comparator 2 event status bit 1 = comparator event occurred 0 = comparator event did not occur bit 8 c1evt: comparator 1 event status bit 1 = comparator event occurred 0 = comparator event did not occur bit 7-3 unimplemented: read as ? 0 ? bit 2 c3out: comparator 3 output status bit when cpol = 0 : 1 = v in + > v in - 0 = v in + < v in - when cpol = 1 : 1 = v in + < v in - 0 = v in + > v in - bit 1 c2out: comparator 2 output status bit when cpol = 0 : 1 = v in + > v in - 0 = v in + < v in - when cpol = 1 : 1 = v in + < v in - 0 = v in + > v in - bit 0 c1out: comparator 1 output status bit when cpol = 0 : 1 = v in + > v in - 0 = v in + < v in - when cpol = 1 : 1 = v in + < v in - 0 = v in + > v in -
? 2011-2014 microchip technology inc. ds70000652f-page 235 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 20-2: cmxcon: comp arator x control register r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 con coe cpol ? ? ?cevtcout bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 evpol1 evpol0 ? cref ? ? cch1 cch0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 con: comparator x enable bit 1 = comparator x is enabled 0 = comparator x is disabled bit 14 coe: comparator x output enable bit 1 = comparator output is present on the cxout pin 0 = comparator output is internal only bit 13 cpol: comparator x output polarity select bit 1 = comparator x output is inverted 0 = comparator x output is not inverted bit 12-10 unimplemented: read as ? 0 ? bit 9 cevt: comparator x event bit 1 = comparator x event according to evpol<1:0> settings occurred; disables future triggers and interrupts until the bit is cleared 0 = comparator x event did not occur bit 8 cout: comparator x output bit when cpol = 0 (non-inverted polarity): 1 = v in + > v in - 0 = v in + < v in - when cpol = 1 (inverted polarity): 1 = v in + < v in - 0 = v in + > v in - bit 7-6 evpol<1:0>: trigger/event/interrupt polarity select bits 11 = trigger/event/interrupt is generated on any change of the comparator output (while cevt = 0 ) 10 = trigger/event/interrupt is generated only on high-to-low transition of the polarity selected comparator output (while cevt = 0 ) if cpol = 1 (inverted polarity): low-to-high transition of the comparator output. if cpol = 0 (non-inverted polarity): high-to-low transition of the comparator output. 01 = trigger/event/interrupt is generated only on low-to-high transition of the polarity selected comparator output (while cevt = 0 ) if cpol = 1 (inverted polarity): high-to-low transition of the comparator output. if cpol = 0 (non-inverted polarity): low-to-high transition of the comparator output. 00 = trigger/event/interrupt generation is disabled bit 5 unimplemented: read as ? 0 ?
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 236 ? 2011-2014 microchip technology inc. bit 4 cref: comparator x reference select bit (v in + input) 1 = v in + input connects to internal cv refin voltage 0 = v in + input connects to cxina pin bit 3-2 unimplemented: read as ? 0 ? bit 1-0 cch<1:0>: comparator x channel select bits 11 = v in - input of comparator connects to intref 10 = v in - input of comparator connects to c x ind pin 01 = v in - input of comparator connects to c x inc pin 00 = v in - input of comparator connects to c x inb pin register 20-2: cmxcon: comparator x control register (continued)
? 2011-2014 microchip technology inc. ds70000652f-page 237 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 20-3: cmxmsksrc: comparator x mask source select register u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 rw-0 ? ? ? ? selsrcc3 selsrcc2 selsrcc1 selsrcc0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 selsrcb3 selsrcb2 selsrcb1 selsrcb0 selsrca3 selsrca2 selsrca1 selsrca0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as ? 0 ? bit 11-8 selsrcc<3:0>: mask c input select bits 1111 = reserved 1110 = reserved 1101 = reserved 1100 = reserved 1011 = reserved 1010 = reserved 1001 = reserved 1000 = reserved 0111 = reserved 0110 = reserved 0101 = pwm1h3 0100 = pwm1l3 0011 = pwm1h2 0010 = pwm1l2 0001 = pwm1h1 0000 = pwm1l1 bit 7-4 selsrcb<3:0>: mask b input select bits 1111 = reserved 1110 = reserved 1101 = reserved 1100 = reserved 1011 = reserved 1010 = reserved 1001 = reserved 1000 = reserved 0111 = reserved 0110 = reserved 0101 = pwm1h3 0100 = pwm1l3 0011 = pwm1h2 0010 = pwm1l2 0001 = pwm1h1 0000 = pwm1l1
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 238 ? 2011-2014 microchip technology inc. bit 3-0 selsrca<3:0>: mask a input select bits 1111 = reserved 1110 = reserved 1101 = reserved 1100 = reserved 1011 = reserved 1010 = reserved 1001 = reserved 1000 = reserved 0111 = reserved 0110 = reserved 0101 = pwm1h3 0100 = pwm1l3 0011 = pwm1h2 0010 = pwm1l2 0001 = pwm1h1 0000 = pwm1l1 register 20-3: cmxmsksrc: comparator x mask source select register (continued)
? 2011-2014 microchip technology inc. ds70000652f-page 239 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 20-4: cmxmskcon: comparator x mask gating control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 hlms ? ocen ocnen oben obnen oaen oanen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nags pags acen acnen aben abnen aaen aanen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 hlms: high or low level masking select bits 1 = the masking (blanking) function will prevent any asserted (? 0 ?) comparator signal from propagating 0 = the masking (blanking) function will prevent any asserted (? 1 ?) comparator signal from propagating bit 14 unimplemented: read as ? 0 ? bit 13 ocen: or gate c input inverted enable bit 1 = mci is connected to or gate 0 = mci is not connected to or gate bit 12 ocnen: or gate c input inverted enable bit 1 = inverted mci is connected to or gate 0 = inverted mci is not connected to or gate bit 11 oben: or gate b input inverted enable bit 1 = mbi is connected to or gate 0 = mbi is not connected to or gate bit 10 obnen: or gate b input inverted enable bit 1 = inverted mbi is connected to or gate 0 = inverted mbi is not connected to or gate bit 9 oaen: or gate a input enable bit 1 = mai is connected to or gate 0 = mai is not connected to or gate bit 8 oanen: or gate a input inverted enable bit 1 = inverted mai is connected to or gate 0 = inverted mai is not connected to or gate bit 7 nags: negative and gate output select 1 = inverted andi is connected to or gate 0 = inverted andi is not connected to or gate bit 6 pags: positive and gate output select 1 = andi is connected to or gate 0 = andi is not connected to or gate bit 5 acen: and gate a1 c input inverted enable bit 1 = mci is connected to and gate 0 = mci is not connected to and gate bit 4 acnen: and gate a1 c input inverted enable bit 1 = inverted mci is connected to and gate 0 = inverted mci is not connected to and gate
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 240 ? 2011-2014 microchip technology inc. bit 3 aben: and gate a1 b input inverted enable bit 1 = mbi is connected to and gate 0 = mbi is not connected to and gate bit 2 abnen: and gate a1 b input inverted enable bit 1 = inverted mbi is connected to and gate 0 = inverted mbi is not connected to and gate bit 1 aaen: and gate a1 a input enable bit 1 = mai is connected to and gate 0 = mai is not connected to and gate bit 0 aanen: and gate a1 a input inverted enable bit 1 = inverted mai is connected to and gate 0 = inverted mai is not connected to and gate register 20-4: cmxmskcon: comparator x mask gating control register (continued)
? 2011-2014 microchip technology inc. ds70000652f-page 241 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 20-5: cmxfltr: comparat or x filter control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? cfsel2 cfsel1 cfsel0 cfltren cfdiv2 cfdiv1 cfdiv0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 cfsel<2:0>: comparator filter input clock select bits 111 = reserved 110 = reserved 101 = timer3 100 = timer2 011 = reserved 010 = pwm special event trigger 001 = f osc 000 = f cy bit 3 cfltren: comparator filter enable bit 1 = digital filter is enabled 0 = digital filter is disabled bit 2-0 cfdiv<2:0>: comparator filter clock divide select bits 111 = clock divide 1:128 110 = clock divide 1:64 101 = clock divide 1:32 100 = clock divide 1:16 011 = clock divide 1:8 010 = clock divide 1:4 001 = clock divide 1:2 000 = clock divide 1:1
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 242 ? 2011-2014 microchip technology inc. register 20-6: cvrcon: comparator vo ltage reference control register u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? vrefsel bgsel1 bgsel0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe ( 1 ) cvrr ? cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10 vrefsel: voltage reference select bit 1 = cv refin = cv ref pin 0 = cv refin is generated by the resistor network bit 9-8 bgsel<1:0>: band gap reference source select bits 11 = intref = cv ref pin 10 = intref = 1.2v (nominal) ( 2 ) 0x = reserved bit 7 cvren: comparator voltage reference enable bit 1 = comparator voltage reference circuit is powered on 0 = comparator voltage reference circuit is powered down bit 6 cvroe: comparator voltage reference output enable bit ( 1 ) 1 = voltage level is output on cv ref pin 0 = voltage level is disconnected from cv ref pin bit 5 cvrr: comparator voltage reference range selection bit 1 = cv rsrc /24 step-size 0 = cv rsrc /32 step-size bit 4 unimplemented: read as ? 0 ? bit 3-0 cvr<3:0>: comparator voltage reference value selection 0 ? cvr<3:0> ? 15 bits when cvrr = 1 : cv refin = (cvr<3:0>/24) ? (cv rsrc ) when cvrr = 0 : cv refin = 1/4 ? (cv rsrc ) + (cvr<3:0>/32) ? (cv rsrc ) note 1: cvroe overrides the trisx bit setting. 2: this reference voltage is generated internally on the device. refer to section 26.0 ?electrical characteristics? for the specified voltage range.
? 2011-2014 microchip technology inc. ds70000652f-page 243 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 21.0 real-time clock and calendar (rtcc) this chapter discusses the real-time clock and calendar (rtcc) module, available on dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices, and its operation. some of the key features of the rtcc module are: ? time: hours, minutes and seconds ? 24-hour format (military time) ? calendar: weekday, date, month and year ? alarm configurable ? year range: 2000 to 2099 ? leap year correction ? bcd format for compact firmware ? optimized for low-power operation ? user calibration with auto-adjust ? calibration range: 2.64 seconds error per month ? requirements: external 32.768 khz clock crystal ? alarm pulse or seconds clock output on rtcc pin the rtcc module is intended for applications where accurate time must be maintained for extended periods of time with minimum to no intervention from the cpu. the rtcc module is optimized for low-power usage to provide extended battery lifetime while keeping track of time. the rtcc module is a 100-year clock and calendar with automatic leap year detection. the range of the clock is from 00:00:00 (midnight) on january 1, 2000 to 23:59:59 on december 31, 2099. the hours are available in 24-hour (military time) format. the clock provides a granularity of one second with half-second visibility to the user. figure 21-1: rt cc block diagram note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 device families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to ?real-time clock and calendar (rtcc)? (ds70310) in the ? dspic33/pic24 family reference man- ual? , which is available on the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. rtcc prescalers rtcc timer comparator compare registers repeat counter with masks rtcc interrupt logic rcfgcal alcfgrpt alarm event 32.768 khz input from sosc oscillator 0.5s rtcc clock domain alarm pulse rtcc interrupt cpu clock domain rtcval alrmval rtcc pin rtcoe
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 244 ? 2011-2014 microchip technology inc. 21.1 rtcc module registers the rtcc module registers are organized into three categories: ? rtcc control registers ? rtcc value registers ? alarm value registers 21.1.1 register mapping to limit the register interface, the rtcc timer and alarm time registers are accessed through corresponding register pointers. the rtcc value register window (rtcvalh and rtcvall) uses the rtcptr bits (rcfgcal<9:8>) to select the desired timer register pair (see table 21-1 ). by writing the rtcvalh byte, the rtcc pointer value (rtcptr<1:0> bits) decrements by one until it reaches ? 00 ?. once it reaches ? 00 ?, the minutes and seconds value will be accessible through rtcvalh and rtcvall until the pointer value is manually changed. table 21-1: rtcval register mapping the alarm value register window (alrmvalh and alrmvall) uses the alrmptr bits (alcfgrpt<9:8>) to select the desired alarm register pair (see ta b l e 2 1 - 2 ). by writing the alrmvalh byte, the alarm pointer value (alrmptr<1:0> bits) decrements by one until it reaches ? 00 ?. once it reaches ? 00 ?, the alrmmin and alrmsec value will be accessible through alrmvalh and alrmvall until the pointer value is manually changed. table 21-2: alrmval register mapping considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the alrmvalh or alrmvall, bytes will decrement the alrmptr<1:0> value. the same applies to the rtcvalh or rtcvall bytes with the rtcptr<1:0> being decremented. 21.1.2 write lock in order to perform a write to any of the rtcc timer registers, the rtcwren bit (rcfgcal<13>) must be set (refer to example 21-1 ). example 21-1: setting the rtcwren bit rtcptr <1:0> rtcc value register window rtcval<15:8> rtcval<7:0> 00 minutes seconds 01 weekday hours 10 month day 11 ? year alrmptr <1:0> alarm value register window alrmval<15:8> alrmval<7:0> 00 alrmmin alrmsec 01 alrmwd alrmhr 10 alrmmnth alrmday 11 ?? note: this only applies to read operations and not write operations. note: to avoid accidental writes to the timer, it is recommended that the rtcwren bit (rcfgcal<13>) is kept clear at any other time. for the rtcwren bit to be set, there is only 1 instruction cycle time window allowed between the 55h/aa sequence and the setting of rtcwren; therefore, it is recommended that code follow the procedure in example 21-1 . mov #nvmkey, w1 ;move the address of nvmkey into w1 mov #0x55, w2 mov #0xaa, w3 mov w2, [w1] ;start 55/aa sequence mov w3, [w1] bset rcfgcal, #13 ;set the rtcwren bit
? 2011-2014 microchip technology inc. ds70000652f-page 245 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 21.2 rtcc control registers register 21-1: rcfgcal: rtcc calibration and configuration register ( 1 ) r/w-0 u-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 rtcen ( 2 ) ? rtcwren rtcsync halfsec ( 3 ) rtcoe rtcptr1 rtcptr0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 rtcen: rtcc enable bit ( 2 ) 1 = rtcc module is enabled 0 = rtcc module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 rtcwren: rtcc value registers write enable bit 1 = rtcvalh and rtcvall registers can be written to by the user 0 = rtcvalh and rtcvall registers are locked out from being written to by the user bit 12 rtcsync: rtcc value registers read synchronization bit 1 = rtcvalh, rtcvall and alcfgrpt registers can change while reading, due to a rollover ripple, resulting in an invalid data read. if the register is read twice and the results are the same data, the data can be assumed to be valid. 0 = rtcvalh, rtcvall or alcfgrpt registers can be read without concern over a rollover ripple bit 11 halfsec: half-second status bit ( 3 ) 1 = second half period of a second 0 = first half period of a second bit 10 rtcoe: rtcc output enable bit 1 = rtcc output is enabled 0 = rtcc output is disabled bit 9-8 rtcptr<1:0>: rtcc value register window pointer bits points to the corresponding rtcc value registers when reading rtcvalh and rtcvall registers; the rtcptr<1:0> value decrements on every read or write of rtcvalh until it reaches ? 00 ?. rtcval<15:8>: 00 = minutes 01 = weekday 10 = month 11 = reserved rtcval<7:0>: 00 = seconds 01 = hours 10 = day 11 = year note 1: the rcfgcal register is only affected by a por. 2: a write to the rtcen bit is only allowed when rtcwren = 1 . 3: this bit is read-only; it is cleared to ? 0 ? on a write to the lower half of the minsec register.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 246 ? 2011-2014 microchip technology inc. bit 7-0 cal<7:0>: rtc drift calibration bits 01111111 = maximum positive adjustment; adds 508 rtc clock pulses every one minute ? ? ? 00000001 = minimum positive adjustment; adds 4 rtc clock pulses every one minute 00000000 = no adjustment 11111111 = minimum negative adjustment; subtracts 4 rtc clock pulses every one minute ? ? ? 10000000 = maximum negative adjustment; subtracts 512 rtc clock pulses every one minute register 21-1: rcfgcal: rtcc calibration and configuration register ( 1 ) (continued) note 1: the rcfgcal register is only affected by a por. 2: a write to the rtcen bit is only allowed when rtcwren = 1 . 3: this bit is read-only; it is cleared to ? 0 ? on a write to the lower half of the minsec register.
? 2011-2014 microchip technology inc. ds70000652f-page 247 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 21-2: padcfg1: pad co nfiguration control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 ? ? ? ? ? ? rtsecsel ( 1 ) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as ? 0 ? bit 1 rtsecsel: rtcc seconds clock output select bit ( 1 ) 1 = rtcc seconds clock is selected for the rtcc pin 0 = rtcc alarm pulse is selected for the rtcc pin bit 0 unimplemented: read as ? 0 ? note 1: to enable the actual rtcc output, the rtcoe (rcfgcal<10>) bit needs to be set.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 248 ? 2011-2014 microchip technology inc. register 21-3: alcfgrpt: al arm configuration register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 alrmen chime amask3 amask2 amask1 amask0 alrmptr1 alrmptr0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 arpt7 arpt6 arpt5 arpt4 arpt3 arpt2 arpt1 arpt0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 alrmen: alarm enable bit 1 = alarm is enabled (cleared automatically after an alarm event whenever arpt<7:0> = 0x00 and chime = 0 ) 0 = alarm is disabled bit 14 chime: chime enable bit 1 = chime is enabled; arpt<7:0> bits are allowed to roll over from 0x00 to 0xff 0 = chime is disabled; arpt<7:0> bits stop once they reach 0x00 bit 13-10 amask<3:0>: alarm mask configuration bits 0000 = every half second 0001 = every second 0010 = every 10 seconds 0011 = every minute 0100 = every 10 minutes 0101 = every hour 0110 = once a day 0111 = once a week 1000 = once a month 1001 = once a year (except when configured for february 29th, once every 4 years) 101x = reserved ? do not use 11xx = reserved ? do not use bit 9-8 alrmptr<1:0>: alarm value register window pointer bits points to the corresponding alarm value registers when reading alrmvalh and alrmvall registers; the alrmptr<1:0> value decrements on every read or write of alrmvalh until it reaches ? 00 ?. alrmval<15:8>: 00 = alrmmin 01 = alrmwd 10 = alrmmnth 11 = unimplemented alrmval<7:0>: 00 = alrmsec 01 = alrmhr 10 = alrmday 11 = unimplemented bit 7-0 arpt<7:0>: alarm repeat counter value bits 11111111 = alarm will repeat 255 more times ? ? ? 00000000 = alarm will not repeat the counter decrements on any alarm event. the counter is prevented from rolling over from 0x00 to 0xff unless chime = 1 .
? 2011-2014 microchip technology inc. ds70000652f-page 249 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 21-4: rtcval (when rtcptr<1:0> = 11 ): rtcc year value register ( 1 ) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x yrten3 yrten2 yrten1 yrten0 yrone3 yrone2 yrone1 yrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-4 yrten<3:0>: binary coded decimal value of year?s tens digit bits contains a value from 0 to 9. bit 3-0 yrone<3:0>: binary coded decimal value of year?s ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 . register 21-5: rtcval (when rtcptr<1:0> = 10 ): rtcc month and day value register ( 1 ) u-0 u-0 u-0 r-x r-x r-x r-x r-x ? ? ? mthten0 mthone3 mthone2 mthone1 mthone0 bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? dayten1 dayten0 dayone3 dayone2 dayone1 dayone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 mthten0: binary coded decimal value of month?s tens digit bit contains a value of 0 or 1. bit 11-8 mthone<3:0>: binary coded decimal value of month?s ones digit bits contains a value from 0 to 9. bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dayten<1:0>: binary coded decimal value of day?s tens digit bits contains a value from 0 to 3. bit 3-0 dayone<3:0>: binary coded decimal value of day?s ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 .
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 250 ? 2011-2014 microchip technology inc. register 21-6: rtcval (when rtcptr<1:0> = 01 ): rtcc weekday and hours value register ( 1 ) u-0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x ? ? ? ? ? wday2 wday1 wday0 bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 wday<2:0>: binary coded decimal value of weekday digit bits contains a value from 0 to 6. bit 7-6 unimplemented: read as ? 0 ? bit 5-4 hrten<1:0>: binary coded decimal value of hour?s tens digit bits contains a value from 0 to 2. bit 3-0 hrone<3:0>: binary coded decimal value of hour?s ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 .
? 2011-2014 microchip technology inc. ds70000652f-page 251 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 21-7: rtcval (when rtcptr<1:0> = 00 ): rtcc minutes and seconds value register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? minten2 minten1 minten0 minone3 minone2 minone1 minone0 bit 15 bit 8 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? secten2 secten1 secten0 secone3 secone2 secone1 secone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 minten<2:0>: binary coded decimal value of minute?s tens digit bits contains a value from 0 to 5. bit 11-8 minone<3:0>: binary coded decimal value of minute?s ones digit bits contains a value from 0 to 9. bit 7 unimplemented: read as ? 0 ? bit 6-4 secten<2:0>: binary coded decimal value of second?s tens digit bits contains a value from 0 to 5. bit 3-0 secone<3:0>: binary coded decimal value of second?s ones digit bits contains a value from 0 to 9.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 252 ? 2011-2014 microchip technology inc. register 21-8: alrmval (when alrmptr<1:0> = 10 ): alarm month and day value register ( 1 ) u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? mthten0 mthone3 mthone2 mthone1 mthone0 bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? dayten1 dayten0 dayone3 dayone2 dayone1 dayone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 mthten0: binary coded decimal value of month?s tens digit bit contains a value of 0 or 1. bit 11-8 mthone<3:0>: binary coded decimal value of month?s ones digit bits contains a value from 0 to 9. bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dayten<1:0>: binary coded decimal value of day?s tens digit bits contains a value from 0 to 3. bit 3-0 dayone<3:0>: binary coded decimal value of day?s ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 .
? 2011-2014 microchip technology inc. ds70000652f-page 253 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 21-9: alrmval (when alrmptr<1:0> = 01 ): alarm weekday and hours value register ( 1 ) u-0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x ? ? ? ? ? wday2 wday1 wday0 bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 wday<2:0>: binary coded decimal value of weekday digit bits contains a value from 0 to 6. bit 7-6 unimplemented: read as ? 0 ? bit 5-4 hrten<1:0>: binary coded decimal value of hour?s tens digit bits contains a value from 0 to 2. bit 3-0 hrone<3:0>: binary coded decimal value of hour?s ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 .
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 254 ? 2011-2014 microchip technology inc. register 21-10: alrmval (when alrmptr<1:0> = 00 ): alarm minutes and seconds value register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? minten2 minten1 minten0 minone3 minone2 minone1 minone0 bit 15 bit 8 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? secten2 secten1 secten0 secone3 secone2 secone1 secone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 minten<2:0>: binary coded decimal value of minute?s tens digit bits contains a value from 0 to 5. bit 11-8 minone<3:0>: binary coded decimal value of minute?s ones digit bits contains a value from 0 to 9. bit 7 unimplemented: read as ? 0 ? bit 6-4 secten<2:0>: binary coded decimal value of second?s tens digit bits contains a value from 0 to 5. bit 3-0 secone<3:0>: binary coded decimal value of second?s ones digit bits contains a value from 0 to 9.
? 2011-2014 microchip technology inc. ds70000652f-page 255 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 22.0 charge time measurement unit (ctmu) the charge time measurement unit (ctmu) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. its key features include: ? four edge input trigger sources ? polarity control for each edge source ? control of edge sequence ? control of response to edges ? precise time measurement resolution of 200 ps ? accurate current source suitable for capacitive measurement ? on-chip temperature measurement using a built-in diode together with other on-chip analog modules, the ctmu can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses that are independent of the system clock. the ctmu module is ideal for interfacing with capacitive-based sensors. the ctmu is controlled through three registers: ctmucon1, ctmucon2 and ctmuicon. ctmucon1 enables the module, the edge delay generation, sequencing of edges, and controls the current source and the output trigger. ctmucon2 controls the edge source selection, edge source polarity selection and edge sampling mode. the ctmuicon register controls the selection and trim of the current source. figure 22-1 shows the ctmu block diagram. note 1: this data sheet summarizes the features of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 device families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to ?charge time measurement unit (ctmu)? (ds70635) in the ? dspic33/pic24 family reference manual? , which is available on the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 256 ? 2011-2014 microchip technology inc. figure 22-1: ctmu block diagram cted1 cted2 current source edge control logic ctmucon1 or ctmucon2 pulse generator ctmui to adc comparator 2 timer1 oc1 current control itrim<5:0> irng<1:0> ctmuicon ctmu control logic edg1stat edg2stat analog-to-digital ctpls ic1 cmp2 c2ina cdelay ctmu temp ctmu temperature sensor current control selection tgen edg1stat, edg2stat ctmu temp 0 edg1stat = edg2stat ctmui 0 edg1stat ? edg2stat ctmup 1 edg1stat ? edg2stat no connect 1 edg1stat = edg2stat trigger tgen ctmup external capacitor for pulse generation
? 2011-2014 microchip technology inc. ds70000652f-page 257 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 22.1 ctmu control registers register 22-1: ctmucon1: ct mu control register 1 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ctmuen ?ctmusidltgen ( 1 ) edgen edgseqen idissen ( 2 ) cttrig bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ctmuen: ctmu enable bit 1 = module is enabled 0 = module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 ctmusidl: ctmu stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12 tgen: time generation enable bit ( 1 ) 1 = enables edge delay generation 0 = disables edge delay generation bit 11 edgen: edge enable bit 1 = edges are not blocked 0 = edges are blocked bit 10 edgseqen: edge sequence enable bit 1 = edge 1 event must occur before edge 2 event can occur 0 = no edge sequence is needed bit 9 idissen: analog current source control bit ( 2 ) 1 = analog current source output is grounded 0 = analog current source output is not grounded bit 8 cttrig: ctmu trigger control bit 1 = trigger output is enabled 0 = trigger output is disabled bit 7-0 unimplemented: read as ? 0 ? note 1: if tgen = 1 , the peripheral inputs and outputs must be configured to an available rpn pin. for more information, see section 10.4 ?peripheral pin select (pps)? . 2: the adc module s&h capacitor is not automatically discharged between sample/conversion cycles. software using the adc as part of a capacitance measurement must discharge the adc capacitor before conducting the measurement. the idissen bit, when set to ? 1 ?, performs this function. the adc must be sampling while the idissen bit is active to connect the discharge sink to the capacitor array.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 258 ? 2011-2014 microchip technology inc. register 22-2: ctmucon2: ct mu control register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 edg1mod edg1pol edg1sel3 edg1sel2 edg 1sel1 edg1sel0 edg2stat edg1stat bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 edg2mod edg2pol edg2sel3 edg2sel2 edg2sel1 edg2sel0 ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 edg1mod: edge 1 edge sampling selection bit 1 = edge 1 is edge-sensitive 0 = edge 1 is level-sensitive bit 14 edg1pol: edge 1 polarity select bit 1 = edge 1 is programmed for a positive edge response 0 = edge 1 is programmed for a negative edge response bit 13-10 edg1sel<3:0>: edge 1 source select bits 1xxx = reserved 01xx = reserved 0011 = cted1 pin 0010 = cted2 pin 0001 = oc1 module 0000 = timer1 module bit 9 edg2stat: edge 2 status bit indicates the status of edge 2 and can be written to control the edge source. 1 = edge 2 has occurred 0 = edge 2 has not occurred bit 8 edg1stat: edge 1 status bit indicates the status of edge 1 and can be written to control the edge source. 1 = edge 1 has occurred 0 = edge 1 has not occurred bit 7 edg2mod: edge 2 edge sampling selection bit 1 = edge 2 is edge-sensitive 0 = edge 2 is level-sensitive bit 6 edg2pol: edge 2 polarity select bit 1 = edge 2 is programmed for a positive edge response 0 = edge 2 is programmed for a negative edge response bit 5-2 edg2sel<3:0>: edge 2 source select bits 1xxx = reserved 01xx = reserved 0011 = cted2 pin 0010 = cted1 pin 0001 = comparator 2 module 0000 = ic1 module bit 1-0 unimplemented: read as ? 0 ?
? 2011-2014 microchip technology inc. ds70000652f-page 259 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 22-3: ctmuicon: ctmu current control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 itrim5 itrim4 itrim3 itrim2 itrim1 itrim0 irng1 irng0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 itrim<5:0>: current source trim bits 011111 = nominal current output specified by irng<1:0> + 62% 011110 = nominal current output specified by irng<1:0> + 60% ? ? ? 000001 = nominal current output specified by irng<1:0> + 2% 000000 = nominal current output specified by irng<1:0> 111111 = nominal current output specified by irng<1:0> ? 2% ? ? ? 100010 = nominal current output specified by irng<1:0> ? 62% 100001 = nominal current output specified by irng<1:0> ? 64% bit 9-8 irng<1:0>: current source range select bits 11 = 100 ? base current ( 1 ) 10 = 10 ? base current 01 = base current level (0.55 ? a nominal) 00 = reserved bit 7-0 unimplemented: read as ? 0 ? note 1: this setting must be used for the ctmu temperature sensor.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 260 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 261 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 23.0 special features dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/ mc)101/102/104 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. these are: ? flexible configuration ? watchdog timer (wdt) ? code protection ? in-circuit serial programming? (icsp?) ? in-circuit emulation 23.1 configuration bits the configuration shadow register bits can be config- ured (read as ? 0 ?) or left unprogrammed (read as ? 1 ?) to select various device configurations. these read-only bits are mapped starting at program memory location, 0xf80000. a detailed explanation of the various bit functions is provided in table 23-4 . note that address, 0xf80000, is beyond the user pro- gram memory space and belongs to the configuration memory space (0x800000-0xffffff), which can only be accessed using table reads. in dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices, the con- figuration bytes are implemented as volatile memory. this means that configuration data must be programmed each time the device is powered up. configuration data is stored in the two words at the top of the on-chip pro- gram memory space, known as the flash configuration words. their specific locations are shown in ta b l e 2 3 - 2 . these are packed representations of the actual device configuration bits, whose actual locations are distributed among several locations in configuration space. the con- figuration data is automatically loaded from the flash configuration words to the proper configuration registers during device resets. when creating applications for these devices, users should always specifically allocate the location of the flash configuration word for configuration data. this is to make certain that program code is not stored in this address when the code is compiled. the upper byte of all flash configuration words in pro- gram memory should always be ? 1111 1111 ?. this makes them appear to be nop instructions in the remote event that their locations are ever executed by accident. since configuration bits are not implemented in the corresponding locations, writing ? 1 ?s to these locations has no effect on device operation. note 1: this data sheet summarizes the features of the dspic33fj16(gp/ mc)101/102 and dspic33fj32(gp/ mc)101/102/104 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to ?programming and diagnostics? (ds70207) and ?device configuration? (ds70194) in the ?dspic33/pic24 family reference manual? , which are available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. note: configuration data is reloaded on all types of device resets. note: performing a page erase operation on the last page of program memory clears the flash configuration words, enabling code protection as a result. therefore, users should avoid performing page erase operations on the last page of program memory.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 262 ? 2011-2014 microchip technology inc. the configuration shadow register map is shown in table 23-1 . the configuration flash word maps are shown in table 23-2 and table 23-3 . table 23-2: configuration flash words for dspic33fj16(gp/mc)10x devices ( 1 ) table 23-3: configuration flash words for dspic33fj32(gp/mc)10x devices ( 1 ) table 23-1: configuration shadow register map file name addr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fgs f80004 ? ? ? ? ? ? gcp gwrp foscsel f80006 ieso pwmlock ( 1 ) ? wdtwin1 wdtwin0 fnosc2 fnosc1 fnosc0 fosc f80008 fcksm1 fcksm0 iol1way ? ? osciofnc poscmd1 poscmd0 fwdt f8000a fwdten windis pllken wdtpre wdtpost3 wdtpost2 wdtpost1 wdtpost0 fpor f8000c pwmpin ( 1 ) hpol ( 1 ) lpol ( 1 ) alti2c1 ? ? ? ? ficd f8000e reserved ( 2 ) ? reserved ( 3 ) reserved ( 3 ) ? ?ics1ics0 legend: ? = unimplemented, read as ? 1 ?. note 1: these bits are available in dspic33fj(16/32)mc10x devices only. 2: this bit is reserved for use by development tools. 3: these bits are reserved, program as ? 0 ?. file name addr. bits 23-16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 config2 002bfc ?iesopwmlock ( 2 ) pwmpin ( 2 ) wdtwin1 wdtwin0 fnosc2 fnosc1 fnosc0 fcksm1 fcksm0 osciofnc ( 5 ) iol1way lpol ( 2 ) alti2c1 poscmd1 poscmd0 config1 002bfe ?reserved ( 3 ) reserved ( 3 ) gcp gwrp reserved ( 4 ) hpol ( 2 ) ics1 ics0 fwdten windis pllken wdtpre wdtpost3 wdtpost2 wdtpost1 wdtpost0 legend: ? = unimplemented, read as ? 1 ?. note 1: during a power-on reset (por), the contents of these flash lo cations are transferred to the configuration shadow registers. 2: these bits are reserved in dspic33fj16gp10x devices and read as ? 1 ?. 3: these bits are reserved, program as ? 0 ?. 4: this bit is reserved for use by development tools and must be programmed as ? 1 ?. 5: this bit is programmed to ? 0 ? during final tests in the factory. file name addr. bits 23-16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 config2 0057fc ? ieso pwmlock ( 2 ) pwmpin ( 2 ) wdtwin1 wdtwin0 fnosc2 fnosc1 fnosc0 fcksm1 fcksm0 osciofnc ( 5 ) iol1way lpol ( 2 ) alti2c1 poscmd1 poscmd0 config1 0057fe ?reserved ( 3 ) reserved ( 3 ) gcp gwrp reserved ( 4 ) hpol ( 2 ) ics1 ics0 fwdten windis pllken wdtpre wdtpost3 wdtpost2 wdtpost1 wdtpost0 legend: ? = unimplemented, read as ? 1 ?. note 1: during a power-on reset (por), the contents of these flash lo cations are transferred to the configuration shadow registers. 2: these bits are reserved in dspic33fj32gp10x devices and read as ? 1 ?. 3: these bits are reserved, program as ? 0 ?. 4: this bit is reserved for use by development tools and must be programmed as ? 1 ?. 5: this bit is programmed to ? 0 ? during final tests in the factory.
? 2011-2014 microchip technology inc. ds70000652f-page 263 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 23-4: dspic33f config uration bits description bit field description gcp general segment code-protect bit 1 = user program memory is not code-protected 0 = code protection is enabled for the entire program memory space gwrp general segment write-protect bit 1 = user program memory is not write-protected 0 = user program memory is write-protected ieso two-speed oscillator start-up enable bit 1 = starts up device with frc, then automatically switches to the user-selected oscillator source when ready 0 = starts up device with user-selected oscillator source pwmlock pwm lock enable bit 1 = certain pwm registers may only be written after a key sequence 0 = pwm registers may be written without a key sequence wdtwin<1:0> watchdog timer window select bits 11 = wdt window is 24% of wdt period 10 = wdt window is 37.5% of wdt period 01 = wdt window is 50% of wdt period 00 = wdt window is 75% of wdt period fnosc<2:0> oscillator selection bits 111 = fast rc oscillator with divide-by-n (frcdivn) 110 = reserved; do not use 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with pll module (ms + pll, ec + pll) 010 = primary oscillator (ms, hs, ec) 001 = fast rc oscillator with divide-by-n and pll module (frcdivn + pll) 000 = fast rc oscillator (frc) fcksm<1:0> clock switching mode bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled iol1way peripheral pin select configuration bit 1 = allow only one reconfiguration 0 = allow multiple reconfigurations osciofnc osc2 pin function bit (except in ms and hs modes) 1 = osc2 is a clock output 0 = osc2 is a general purpose digital i/o pin poscmd<1:0> primary oscillator mode select bits 11 = primary oscillator is disabled 10 = hs crystal oscillator mode (10 mhz-32 mhz) 01 = ms crystal oscillator mode (3 mhz-10 mhz) 00 = ec (external clock) mode (dc-32 mhz) fwdten watchdog timer enable bit 1 = watchdog timer is always enabled (lprc oscillator cannot be disabled; clearing the swdten bit in the rcon register will have no effect) 0 = watchdog timer is enabled/disabled by user software (lprc can be disabled by clearing the swdten bit in the rcon register) windis watchdog timer window enable bit 1 = watchdog timer in non-window mode 0 = watchdog timer in window mode
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 264 ? 2011-2014 microchip technology inc. wdtpre watchdog timer prescaler bit 1 = 1:128 0 = 1:32 wdtpost<3:0> watchdog timer postscaler bits 1111 = 1:32,768 1110 = 1:16,384 ? ? ? 0001 = 1:2 0000 = 1:1 pllken pll lock enable bit 1 = clock switch to pll will wait until the pll lock signal is valid 0 = clock switch will not wait for the pll lock signal alti2c alternate i 2 c? pins bit 1 = i 2 c is mapped to sda1/scl1 pins 0 = i 2 c is mapped to asda1/ascl1 pins ics<1:0> icd communication channel select bits 11 = communicate on pgec1 and pged1 10 = communicate on pgec2 and pged2 01 = communicate on pgec3 and pged3 00 = reserved, do not use pwmpin motor control pwm module pin mode bit 1 = pwm module pins controlled by port register at device reset (tri-stated) 0 = pwm module pins controlled by pwm module at device reset (configured as output pins) hpol motor control pwm high side polarity bit 1 = pwm module high side output pins have active-high output polarity 0 = pwm module high side output pins have active-low output polarity lpol motor control pwm low side polarity bit 1 = pwm module low side output pins have active-high output polarity 0 = pwm module low side output pins have active-low output polarity table 23-4: dspic33f configuration bits description (continued) bit field description
? 2011-2014 microchip technology inc. ds70000652f-page 265 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 register 23-1: devid: device id register rrrrrrrr devid<23:16> ( 1 ) bit 23 bit 16 rrrrrrrr devid<15:8> ( 1 ) bit 15 bit 8 rrrrrrrr devid<7:0> ( 1 ) bit 7 bit 0 legend: r = read-only bit u = unimplemented bit bit 23-0 deidv<23:0>: device identifier bits ( 1 ) note 1: refer to the ?dspic33f flash programming specification for devices with volatile configuration bits? (ds70659) for the list of device id values. register 23-2: devrev: device revision register rrrrrrrr devrev<23:16> ( 1 ) bit 23 bit 16 rrrrrrrr devrev<15:8> ( 1 ) bit 15 bit 8 rrrrrrrr devrev<7:0> ( 1 ) bit 7 bit 0 legend: r = read-only bit u = unimplemented bit bit 23-0 devrev<23:0>: device revision bits ( 1 ) note 1: refer to the ?dspic33f flash programming specification for devices with volatile configuration bits? (ds70659) for the list of device revision values.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 266 ? 2011-2014 microchip technology inc. 23.2 on-chip voltage regulator all of the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices power their core digital logic at a nominal 2.5v. this can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3v. to simplify system design, all devices in the dspic33fj16(gp/ mc)101/102 and dspic33fj32(gp/mc)101/102/104 family incorporate an on-chip regulator that allows the device to run its core logic from v dd . the regulator provides power to the core from the other v dd pins. when the regulator is enabled, a low-esr (less than 5 ohms) capacitor (such as tantalum or ceramic) must be connected to the v cap pin ( figure 23-1 ). this helps to maintain the stability of the regulator. the recommended value for the filter capac- itor is provided in table 26-14 located in section 26.1 ?dc characteristics? . on a por , it takes approximately 20 ? s for the on-chip voltage regulator to generate an output voltage. during this time, designated as t startup , code execution is disabled. t startup is applied every time the device resumes operation after any power-down. figure 23-1: conne ctions for the on-chip voltage regulator ( 1 , 2 , 3 ) 23.3 bor: brown-out reset the brown-out reset (bor) module is based on an internal voltage reference circuit that monitors the regulated supply voltage, v cap . the main purpose of the bor module is to generate a device reset when a brown-out condition occurs. brown-out conditions are generally caused by glitches on the ac mains (for example, missing portions of the ac cycle waveform due to bad power transmission lines or voltage sags due to excessive current draw when a large inductive load is turned on). a bor generates a reset pulse, which resets the device. the bor selects the clock source, based on the device configuration bit values (fnosc<2:0> and poscmd<1:0>). if an oscillator mode is selected, the bor activates the oscillator start-up timer (ost). the system clock is held until ost expires. if the pll is used, the clock is held until the lock bit (osccon<5>) is ? 1 ?. concurrently, the pwrt time-out (t pwrt ) is applied before the internal reset is released. if t pwrt = 0 and a crystal oscillator is being used, then a nominal delay of t fscm = 100 is applied. the total delay in this case is t fscm . the bor status bit (rcon<1>) is set to indicate that a bor has occurred. the bor circuit continues to oper- ate while in sleep or idle modes and resets the device should v dd fall below the bor threshold voltage. note: it is important for low-esr capacitors to be placed as close as possible to the v cap pin. note 1: these are typical operating voltages. refer to table 26-14 located in section 26.1 ?dc characteristics? for the full operating ranges of v dd and v cap . 2: it is important for low-esr capacitors to be placed as close as possible to the v cap pin. 3: typical v cap pin voltage = 2.5v when v dd ? v ddmin . v dd v cap v ss dspic33f c efc 3.3v 10 f tantalum
? 2011-2014 microchip technology inc. ds70000652f-page 267 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 23.4 watchdog timer (wdt) for dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 devices, the wdt is driven by the lprc oscillator. when the wdt is enabled, the clock source is also enabled. 23.4.1 prescaler/postscaler the nominal wdt clock source from lprc is 32 khz. this feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. the prescaler is set by the wdtpre configuration bit. with a 32 khz input, the prescaler yields a nominal wdt time-out (t wdt ) period of 1 ms in 5-bit mode or 4 ms in 7-bit mode. a variable postscaler divides down the wdt prescaler output and allows for a wide range of time-out periods. the postscaler is controlled by the wdtpost<3:0> configuration bits (fwdt<3:0>), which allow the selection of 16 settings, from 1:1 to 1:32,768. using the prescaler and postscaler, time-out periods, ranging from 1 ms to 131 seconds, can be achieved. the wdt, prescaler and postscaler are reset: ? on any device reset ? on the completion of a clock switch, whether invoked by software (i.e., setting the oswen bit after changing the noscx bits) or by hardware (i.e., fail-safe clock monitor) ? when a pwrsav instruction is executed (i.e., sleep or idle mode is entered) ? when the device exits sleep or idle mode to resume normal operation ?by a clrwdt instruction during normal execution 23.4.2 sleep and idle modes if the wdt is enabled, it will continue to run during sleep or idle modes. when the wdt time-out occurs, the device will wake the device and code execution will continue from where the pwrsav instruction was executed. the corresponding sleep or idle bits (rcon<3:2>) will need to be cleared in software after the device wakes up. 23.4.3 enabling wdt the wdt is enabled or disabled by the fwdten configuration bit in the fwdt configuration register. when the fwdten configuration bit is set, the wdt is always enabled. the wdt can be optionally controlled in software when the fwdten configuration bit has been programmed to ? 0 ?. the wdt is enabled in software by setting the swdten control bit (rcon<5>). the swdten control bit is cleared on any device reset. the software wdt option allows the user application to enable the wdt for critical code segments and disables the wdt during non-critical segments for maximum power savings. the wdt flag bit, wdto (rcon<4>), is not automatically cleared following a wdt time-out. to detect subsequent wdt events, the flag must be cleared in software. figure 23-2: wdt block diagram note: the clrwdt and pwrsav instructions clear the prescaler and postscaler counts when executed. note: if the windis bit (fwdt<6>) is cleared, the clrwdt instruction should be executed by the application software only during the last 1/4 of the wdt period. this clrwdt window can be determined by using a timer. if a clrwdt instruction is executed before this window, a wdt reset occurs. 0 1 wdtpre wdtpost<3:0> watchdog timer prescaler (divide-by-n1) postscaler (divide-by-n2) sleep/idle wdt wdt window select windis wdt clrwdt instruction swdten fwdten lprc clock rs rs wake-up reset all device resets transition to new clock source exit sleep or idle mode pwrsav instruction clrwdt instruction
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 268 ? 2011-2014 microchip technology inc. 23.5 in-circuit serial programming? (icsp?) devices can be serially programmed while in the end application circuit. this is done with two lines for clock and data and three other lines for power, ground and the programming sequence. serial programming allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. serial programming also allows the most recent firmware or a custom firmware to be programmed. refer to the ?dspic33f flash programming specification for devices with volatile configuration bits? (ds70659) for details about in-circuit serial programming (icsp). any of the three pairs of programming clock/data pins can be used: ? pgec1 and pged1 ? pgec2 and pged2 ? pgec3 and pged3 23.6 in-circuit debugger when mplab ? icd 3 is selected as a debugger, the in- circuit debugging functionality is enabled. this function allows simple debugging functions when used with mplab ide. debugging functionality is controlled through the pgecx (emulation/debug clock) and pgedx (emulation/debug data) pin functions. any of the three pairs of debugging clock/data pins can be used: ? pgec1 and pged1 ? pgec2 and pged2 ? pgec3 and pged3 to use the in-circuit debugger function of the device, the design must implement icsp connections to mclr , v dd , v ss and the pgecx/pgedx pin pair. in addition, when the feature is enabled, some of the resources are not available for general use. these resources include the first 80 bytes of data ram and two i/o pins.
? 2011-2014 microchip technology inc. ds70000652f-page 269 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 24.0 instruction set summary the dspic33f instruction set is identical to that of the dspic30f. most instructions are a single program memory word (24 bits). only three instructions require two program memory locations. each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into five basic categories: ? word or byte-oriented operations ? bit-oriented operations ? literal operations ? dsp operations ? control operations table 24-1 shows the general symbols used in describing the instructions. the dspic33f instruction set summary in tab l e 2 4- 2 lists all the instructions, along with the status flags affected by each instruction. most word or byte-oriented w register instructions (including barrel shift instructions) have three operands: ? the first source operand, which is typically a register ?wb? without any address modifier ? the second source operand, which is typically a register ?ws? with or without an address modifier ? the destination of the result, which is typically a register ?wd? with or without an address modifier however, word or byte-oriented file register instructions have two operands: ? the file register specified by the value ?f? ? the destination, which could be either the file register ?f? or the w0 register, which is denoted as ?wreg? most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: ? the w register (with or without an address modifier) or file register (specified by the value of ?ws? or ?f?) ? the bit in the w register or file register (specified by a literal value or indirectly by the contents of register ?wb?) the literal instructions that involve data movement can use some of the following operands: ? a literal value to be loaded into a w register or file register (specified by ?k?) ? the w register or file register where the literal value is to be loaded (specified by ?wb? or ?f?) however, literal instructions that involve arithmetic or logical operations use some of the following operands: ? the first source operand, which is a register ?wb? without any address modifier ? the second source operand, which is a literal value ? the destination of the result (only if not the same as the first source operand), which is typically a register ?wd? with or without an address modifier the mac class of dsp instructions can use some of the following operands: ? the accumulator (a or b) to be used (required operand) ? the w registers to be used as the two operands ? the x and y address space prefetch operations ? the x and y address space prefetch destinations ? the accumulator write-back destination the other dsp instructions do not involve any multiplication and can include: ? the accumulator to be used (required) ? the source or destination operand (designated as wso or wdo, respectively) with or without an address modifier ? the amount of shift specified by a w register ?wn? or a literal value the control instructions can use some of the following operands: ? a program memory address ? the mode of the table read and table write instructions note: this data sheet summarizes the features of the dspic33fj16(gp/ mc)101/102 and dspic33fj32(gp/ mc)101/102/104 devices. however, it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the latest family reference sections of the ?dspic33/pic24 family reference manual? , which are available from the microchip web site ( www.microchip.com ).
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 270 ? 2011-2014 microchip technology inc. most instructions are a single word. certain double- word instructions are designed to provide all the required information in these 48 bits. in the second word, the 8 msbs are ? 0 ?s. if this second word is executed as an instruction (by itself), it will execute as a nop . the double-word instructions execute in two instruction cycles. most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . notable exceptions are the bra (uncondi- tional/computed branch), indirect call/goto , all table reads and writes and return/retfie instructions, which are single-word instructions but take two or three cycles. certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. moreover, double-word moves require two cycles. note: for more details on the instruction set, refer to the ?16-bit mcu and dsc programmer?s reference manual? (ds70157). table 24-1: symbols used in opcode descriptions field description #text means literal defined by ? text ? (text) means ?content of text ? [text] means ?the location addressed by text ? { } optional field or operation register bit field .b byte mode selection .d double-word mode selection .s shadow register select .w word mode selection (default) acc one of two accumulators {a, b} awb accumulator write-back destination address register ?? {w13, [w13]+ = 2} bit4 4-bit bit selection field (used in word addressed instructions) ?? {0...15} c, dc, n, ov, z mcu status bits: carry, digit carry, negative, overflow, sticky zero expr absolute address, label or expression (resolved by the linker) f file register address ?? {0x0000...0x1fff} lit1 1-bit unsigned literal ?? {0,1} lit4 4-bit unsigned literal ?? {0...15} lit5 5-bit unsigned literal ?? {0...31} lit8 8-bit unsigned literal ?? {0...255} lit10 10-bit unsigned literal ?? {0...255} for byte mode, {0:1023} for word mode lit14 14-bit unsigned literal ?? {0...16384} lit16 16-bit unsigned literal ?? {0...65535} lit23 23-bit unsigned literal ?? {0...8388608}; lsb must be ? 0 ? none field does not require an entry, can be blank oa, ob, sa, sb dsp status bits: acca overflow, accb overflow, acca saturate, accb saturate pc program counter slit10 10-bit signed literal ?? {-512...511} slit16 16-bit signed literal ?? {-32768...32767} slit6 6-bit signed literal ?? {-16...16} wb base w register ?? {w0..w15} wd destination w register ?? { wd, [wd], [wd++], [wd--], [++wd], [--wd] } wdo destination w register ?? { wnd, [wnd], [wnd++], [wnd--], [++wnd], [--wnd], [wnd+wb] } wm, wn dividend, divisor working r egister pair (direct addressing)
? 2011-2014 microchip technology inc. ds70000652f-page 271 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 wm*wm multiplicand and multiplier working register pair for square instructions ?? {w4 * w4,w5 * w5,w6 * w6,w7 * w7} wm*wn multiplicand and multiplier working register pair for dsp instructions ? {w4 * w5,w4 * w6,w4 * w7,w5 * w6,w5 * w7,w6 * w7} wn one of 16 working registers ?? {w0..w15} wnd one of 16 destination working registers ?? {w0..w15} wns one of 16 source working registers ?? {w0..w15} wreg w0 (working register used in file register instructions) ws source w register ?? { ws, [ws], [ws++], [ws--], [++ws], [--ws] } wso source w register ?? { wns, [wns], [wns++], [wns--], [++wns], [--wns], [wns+wb] } wx x data space prefetch address register for dsp instructions ? {[w8] + = 6, [w8] + = 4, [w8] + = 2, [w8], [w8] - = 6, [w8] - = 4, [w8] - = 2, [w9] + = 6, [w9] + = 4, [w9] + = 2, [w9], [w9] - = 6, [w9] - = 4, [w9] - = 2, [w9 + w12], none} wxd x data space prefetch destination register for dsp instructions ?? {w4..w7} wy y data space prefetch address register for dsp instructions ? {[w10] + = 6, [w10] + = 4, [w10] + = 2, [w10], [w10] - = 6, [w10] - = 4, [w10] - = 2, [w11] + = 6, [w11] + = 4, [w11] + = 2, [w11], [w11] - = 6, [w11] - = 4, [w11] - = 2, [w11 + w12], none} wyd y data space prefetch destination register for dsp instructions ?? {w4..w7} table 24-1: symbols used in opcode descriptions (continued) field description
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 272 ? 2011-2014 microchip technology inc. table 24-2: instruction set overview base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected 1 add add acc add accumulators 1 1 oa,ob,sa,sb add f f = f + wreg 1 1 c,dc,n,ov,z add f,wreg wreg = f + wreg 1 1 c,dc,n,ov,z add #lit10,wn wd = lit10 + wd 1 1 c,dc,n,ov,z add wb,ws,wd wd = wb + ws 1 1 c,dc,n,ov,z add wb,#lit5,wd wd = wb + lit5 1 1 c,dc,n,ov,z add wso,#slit4,acc 16-bit signed add to accumulator 1 1 oa,ob,sa,sb 2 addc addc f f = f + wreg + (c) 1 1 c,dc,n,ov,z addc f,wreg wreg = f + wreg + (c) 1 1 c,dc,n,ov,z addc #lit10,wn wd = lit10 + wd + (c) 1 1 c,dc,n,ov,z addc wb,ws,wd wd = wb + ws + (c) 1 1 c,dc,n,ov,z addc wb,#lit5,wd wd = wb + lit5 + (c) 1 1 c,dc,n,ov,z 3 and and f f = f .and. wreg 1 1 n,z and f,wreg wreg = f .and. wreg 1 1 n,z and #lit10,wn wd = lit10 .and. wd 1 1 n,z and wb,ws,wd wd = wb .and. ws 1 1 n,z and wb,#lit5,wd wd = wb .and. lit5 1 1 n,z 4 asr asr f f = arithmetic right shift f 1 1 c,n,ov,z asr f,wreg wreg = arithmetic right shift f 1 1 c,n,ov,z asr ws,wd wd = arithmetic right shift ws 1 1 c,n,ov,z asr wb,wns,wnd wnd = arithmetic right shift wb by wns 1 1 n,z asr wb,#lit5,wnd wnd = arithmetic right shift wb by lit5 1 1 n,z 5 bclr bclr f,#bit4 bit clear f 1 1 none bclr ws,#bit4 bit clear ws 1 1 none 6 bra bra c,expr branch if carry 1 1 (2) none bra ge,expr branch if greater than or equal 1 1 (2) none bra geu,expr branch if unsigned greater than or equal 1 1 (2) none bra gt,expr branch if greater than 1 1 (2) none bra gtu,expr branch if unsigned greater than 1 1 (2) none bra le,expr branch if less than or equal 1 1 (2) none bra leu,expr branch if unsigned less than or equal 1 1 (2) none bra lt,expr branch if less than 1 1 (2) none bra ltu,expr branch if unsigned less than 1 1 (2) none bra n,expr branch if negative 1 1 (2) none bra nc,expr branch if not carry 1 1 (2) none bra nn,expr branch if not negative 1 1 (2) none bra nov,expr branch if not overflow 1 1 (2) none bra nz,expr branch if not zero 1 1 (2) none bra oa,expr branch if accumulator a overflow 1 1 (2) none bra ob,expr branch if accumulator b overflow 1 1 (2) none bra ov,expr branch if overflow 1 1 (2) none bra sa,expr branch if accumulator a saturated 1 1 (2) none bra sb,expr branch if accumulator b saturated 1 1 (2) none bra expr branch unconditionally 1 2 none bra z,expr branch if zero 1 1 (2) none bra wn computed branch 1 2 none 7 bset bset f,#bit4 bit set f 1 1 none bset ws,#bit4 bit set ws 1 1 none 8 bsw bsw.c ws,wb write c bit to ws 1 1 none bsw.z ws,wb write z bit to ws 1 1 none
? 2011-2014 microchip technology inc. ds70000652f-page 273 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 9 btg btg f,#bit4 bit toggle f 1 1 none btg ws,#bit4 bit toggle ws 1 1 none 10 btsc btsc f,#bit4 bit test f, skip if clear 1 1 (2 or 3) none btsc ws,#bit4 bit test ws, skip if clear 1 1 (2 or 3) none 11 btss btss f,#bit4 bit test f, skip if set 1 1 (2 or 3) none btss ws,#bit4 bit test ws, skip if set 1 1 (2 or 3) none 12 btst btst f,#bit4 bit test f 1 1 z btst.c ws,#bit4 bit test ws to c 1 1 c btst.z ws,#bit4 bit test ws to z 1 1 z btst.c ws,wb bit test ws to c 1 1 c btst.z ws,wb bit test ws to z 1 1 z 13 btsts btsts f,#bit4 bit test then set f 1 1 z btsts.c ws,#bit4 bit test ws to c, then set 1 1 c btsts.z ws,#bit4 bit test ws to z, then set 1 1 z 14 call call lit23 call subroutine 2 2 none call wn call indirect subroutine 1 2 none 15 clr clr f f = 0x0000 1 1 none clr wreg wreg = 0x0000 1 1 none clr ws ws = 0x0000 1 1 none clr acc,wx,wxd,wy,wyd,awb clear accumulator 1 1 oa,ob,sa,sb 16 clrwdt clrwdt clear watchdog timer 1 1 wdto,sleep 17 com com f f = f 11 n,z com f,wreg wreg = f 11 n,z com ws,wd wd = ws 11 n,z 18 cp cp f compare f with wreg 1 1 c,dc,n,ov,z cp wb,#lit5 compare wb with lit5 1 1 c,dc,n,ov,z cp wb,ws compare wb with ws (wb ? ws) 1 1 c,dc,n,ov,z 19 cp0 cp0 f compare f with 0x0000 1 1 c,dc,n,ov,z cp0 ws compare ws with 0x0000 1 1 c,dc,n,ov,z 20 cpb cpb f compare f with wreg, with borrow 1 1 c,dc,n,ov,z cpb wb,#lit5 compare wb with lit5, with borrow 1 1 c,dc,n,ov,z cpb wb,ws compare wb with ws, with borrow (wb ? ws ? c ) 1 1 c,dc,n,ov,z 21 cpseq cpseq wb, wn compare wb with wn, skip if = 1 1 (2 or 3) none 22 cpsgt cpsgt wb, wn compare wb with wn, skip if > 1 1 (2 or 3) none 23 cpslt cpslt wb, wn compare wb with wn, skip if < 1 1 (2 or 3) none 24 cpsne cpsne wb, wn compare wb with wn, skip if ? 11 (2 or 3) none 25 daw daw wn wn = decimal adjust wn 1 1 c 26 dec dec f f = f ? 1 1 1 c,dc,n,ov,z dec f,wreg wreg = f ? 1 1 1 c,dc,n,ov,z dec ws,wd wd = ws ? 1 1 1 c,dc,n,ov,z 27 dec2 dec2 f f = f ? 2 1 1 c,dc,n,ov,z dec2 f,wreg wreg = f ? 2 1 1 c,dc,n,ov,z dec2 ws,wd wd = ws ? 2 1 1 c,dc,n,ov,z 28 disi disi #lit14 disable interrupts for k instruction cycles 1 1 none table 24-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 274 ? 2011-2014 microchip technology inc. 29 div div.s wm,wn signed 16/16-bit integer divide 1 18 n,z,c,ov div.sd wm,wn signed 32/16-bit integer divide 1 18 n,z,c,ov div.u wm,wn unsigned 16/16-bit integer divide 1 18 n,z,c,ov div.ud wm,wn unsigned 32/16-bit integer divide 1 18 n,z,c,ov 30 divf divf wm,wn signed 16/16-bit fractional divide 1 18 n,z,c,ov 31 do do #lit14,expr do code to pc + expr, lit14 + 1 times 2 2 none do wn,expr do code to pc + expr, (wn) + 1 times 2 2 none 32 ed ed wm*wm,acc,wx,wy,wxd euclidean distance (no accumulate) 1 1 oa,ob,oab, sa,sb,sab 33 edac edac wm*wm,acc,wx,wy,wxd euclidean distance 1 1 oa,ob,oab, sa,sb,sab 34 exch exch wns,wnd swap wns with wnd 1 1 none 35 fbcl fbcl ws,wnd find bit change from left (msb) side 1 1 c 36 ff1l ff1l ws,wnd find first one from left (msb) side 1 1 c 37 ff1r ff1r ws,wnd find first one from right (lsb) side 1 1 c 38 goto goto expr go to address 2 2 none goto wn go to indirect 1 2 none 39 inc inc f f = f + 1 1 1 c,dc,n,ov,z inc f,wreg wreg = f + 1 1 1 c,dc,n,ov,z inc ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 40 inc2 inc2 f f = f + 2 1 1 c,dc,n,ov,z inc2 f,wreg wreg = f + 2 1 1 c,dc,n,ov,z inc2 ws,wd wd = ws + 2 1 1 c,dc,n,ov,z 41 ior ior f f = f .ior. wreg 1 1 n,z ior f,wreg wreg = f .ior. wreg 1 1 n,z ior #lit10,wn wd = lit10 .ior. wd 1 1 n,z ior wb,ws,wd wd = wb .ior. ws 1 1 n,z ior wb,#lit5,wd wd = wb .ior. lit5 1 1 n,z 42 lac lac wso,#slit4,acc load accumulator 1 1 oa,ob,oab, sa,sb,sab 43 lnk lnk #lit14 link frame pointer 1 1 none 44 lsr lsr f f = logical right shift f 1 1 c,n,ov,z lsr f,wreg wreg = logical right shift f 1 1 c,n,ov,z lsr ws,wd wd = logical right shift ws 1 1 c,n,ov,z lsr wb,wns,wnd wnd = logical right shift wb by wns 1 1 n,z lsr wb,#lit5,wnd wnd = logical right shift wb by lit5 1 1 n,z 45 mac mac wm*wn,acc,wx,wxd,wy,wyd, awb multiply and accumulate 1 1 oa,ob,oab, sa,sb,sab mac wm*wm,acc,wx,wxd,wy,wyd square and accumulate 1 1 oa,ob,oab, sa,sb,sab 46 mov mov f,wn move f to wn 1 1 none mov f move f to f 1 1 n,z mov f,wreg move f to wreg 1 1 none mov #lit16,wn move 16-bit literal to wn 1 1 none mov.b #lit8,wn move 8-bit literal to wn 1 1 none mov wn,f move wn to f 1 1 none mov wso,wdo move ws to wd 1 1 none mov wreg,f move wreg to f 1 1 none mov.d wns,wd move double from w(ns):w(ns + 1) to wd 1 2 none mov.d ws,wnd move double from ws to w(nd + 1):w(nd) 1 2 none 47 movsac movsac acc,wx,wxd,wy,wyd,awb prefetch and store accumulator 1 1 none table 24-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected
? 2011-2014 microchip technology inc. ds70000652f-page 275 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 48 mpy mpy wm*wn,acc,wx,wxd,wy,wyd multiply wm by wn to accumulator 1 1 oa,ob,oab, sa,sb,sab mpy wm*wm,acc,wx,wxd,wy,wyd square wm to accumulator 1 1 oa,ob,oab, sa,sb,sab 49 mpy.n mpy.n wm*wn,acc,wx,wxd,wy,wyd (multiply wm by wn) to accumulator 1 1 none 50 msc msc wm*wm,acc,wx,wxd,wy,wyd, awb multiply and subtract from accumulator 1 1 oa,ob,oab, sa,sb,sab 51 mul mul.ss wb,ws,wnd {wnd + 1, wnd} = signed(wb) * signed(ws) 1 1 none mul.su wb,ws,wnd {wnd + 1, wnd} = signed(wb) * unsigned(ws) 1 1 none mul.us wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * signed(ws) 1 1 none mul.uu wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(ws) 11 none mul.su wb,#lit5,wnd {wnd + 1, wnd} = signed(wb) * unsigned(lit5) 1 1 none mul.uu wb,#lit5,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(lit5) 11 none mul f w3:w2 = f * wreg 1 1 none 52 neg neg acc negate accumulator 1 1 oa,ob,oab, sa,sb,sab neg f f = f + 1 1 1 c,dc,n,ov,z neg f,wreg wreg = f + 1 1 1 c,dc,n,ov,z neg ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 53 nop nop no operation 1 1 none nopr no operation 1 1 none 54 pop pop f pop f from top-of-stack (tos) 1 1 none pop wdo pop from top-of-stack (tos) to wdo 1 1 none pop.d wnd pop from top-of-stack (tos) to w(nd):w(nd + 1) 12 none pop.s pop shadow registers 1 1 all 55 push push f push f to top-of-stack (tos) 1 1 none push wso push wso to top-of-stack (tos) 1 1 none push.d wns push w(ns):w(ns + 1) to top-of-stack (tos) 1 2 none push.s push shadow registers 1 1 none 56 pwrsav pwrsav #lit1 go into sleep or idle mode 1 1 wdto,sleep 57 rcall rcall expr relative call 1 2 none rcall wn computed call 1 2 none 58 repeat repeat #lit14 repeat next instruction lit14 + 1 times 1 1 none repeat wn repeat next instruction (wn) + 1 times 1 1 none 59 reset reset software device reset 1 1 none 60 retfie retfie return from interrupt 1 3 (2) none 61 retlw retlw #lit10,wn return with literal in wn 1 3 (2) none 62 return return return from subroutine 1 3 (2) none 63 rlc rlc f f = rotate left through carry f 1 1 c,n,z rlc f,wreg wreg = rotate left through carry f 1 1 c,n,z rlc ws,wd wd = rotate left through carry ws 1 1 c,n,z 64 rlnc rlnc f f = rotate left (no carry) f 1 1 n,z rlnc f,wreg wreg = rotate left (no carry) f 1 1 n,z rlnc ws,wd wd = rotate left (no carry) ws 1 1 n,z 65 rrc rrc f f = rotate right through carry f 1 1 c,n,z rrc f,wreg wreg = rotate right through carry f 1 1 c,n,z rrc ws,wd wd = rotate right through carry ws 1 1 c,n,z table 24-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 276 ? 2011-2014 microchip technology inc. 66 rrnc rrnc f f = rotate right (no carry) f 1 1 n,z rrnc f,wreg wreg = rotate right (no carry) f 1 1 n,z rrnc ws,wd wd = rotate right (no carry) ws 1 1 n,z 67 sac sac acc,#slit4,wdo store accumulator 1 1 none sac.r acc,#slit4,wdo store rounded accumulator 1 1 none 68 se se ws,wnd wnd = sign-extended ws 1 1 c,n,z 69 setm setm f f = 0xffff 1 1 none setm wreg wreg = 0xffff 1 1 none setm ws ws = 0xffff 1 1 none 70 sftac sftac acc,wn arithmetic shift accumulator by (wn) 1 1 oa,ob,oab, sa,sb,sab sftac acc,#slit6 arithmetic shift accumulator by slit6 1 1 oa,ob,oab, sa,sb,sab 71 sl sl f f = left shift f 1 1 c,n,ov,z sl f,wreg wreg = left shift f 1 1 c,n,ov,z sl ws,wd wd = left shift ws 1 1 c,n,ov,z sl wb,wns,wnd wnd = left shift wb by wns 1 1 n,z sl wb,#lit5,wnd wnd = left shift wb by lit5 1 1 n,z 72 sub sub acc subtract accumulators 1 1 oa,ob,oab, sa,sb,sab sub f f = f ? wreg 1 1 c,dc,n,ov,z sub f,wreg wreg = f ? wreg 1 1 c,dc,n,ov,z sub #lit10,wn wn = wn ? lit10 1 1 c,dc,n,ov,z sub wb,ws,wd wd = wb ? ws 1 1 c,dc,n,ov,z sub wb,#lit5,wd wd = wb ? lit5 1 1 c,dc,n,ov,z 73 subb subb f f = f ? wreg ? (c ) 1 1 c,dc,n,ov,z subb f,wreg wreg = f ? wreg ? (c ) 1 1 c,dc,n,ov,z subb #lit10,wn wn = wn ? lit10 ? (c ) 1 1 c,dc,n,ov,z subb wb,ws,wd wd = wb ? ws ? (c ) 1 1 c,dc,n,ov,z subb wb,#lit5,wd wd = wb ? lit5 ? (c ) 1 1 c,dc,n,ov,z 74 subr subr f f = wreg ? f 1 1 c,dc,n,ov,z subr f,wreg wreg = wreg ? f 1 1 c,dc,n,ov,z subr wb,ws,wd wd = ws ? wb 1 1 c,dc,n,ov,z subr wb,#lit5,wd wd = lit5 ? wb 1 1 c,dc,n,ov,z 75 subbr subbr f f = wreg ? f ? (c ) 1 1 c,dc,n,ov,z subbr f,wreg wreg = wreg ? f ? (c ) 1 1 c,dc,n,ov,z subbr wb,ws,wd wd = ws ? wb ? (c ) 1 1 c,dc,n,ov,z subbr wb,#lit5,wd wd = lit5 ? wb ? (c ) 1 1 c,dc,n,ov,z 76 swap swap.b wn wn = nibble swap wn 1 1 none swap wn wn = byte swap wn 1 1 none 77 tblrdh tblrdh ws,wd read prog<23:16> to wd<7:0> 1 2 none 78 tblrdl tblrdl ws,wd read prog<15:0> to wd 1 2 none 79 tblwth tblwth ws,wd write ws<7:0> to prog<23:16> 1 2 none 80 tblwtl tblwtl ws,wd write ws to prog<15:0> 1 2 none 81 ulnk ulnk unlink frame pointer 1 1 none 82 xor xor f f = f .xor. wreg 1 1 n,z xor f,wreg wreg = f .xor. wreg 1 1 n,z xor #lit10,wn wd = lit10 .xor. wd 1 1 n,z xor wb,ws,wd wd = wb .xor. ws 1 1 n,z xor wb,#lit5,wd wd = wb .xor. lit5 1 1 n,z 83 ze ze ws,wnd wnd = zero-extend ws 1 1 c,z,n table 24-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected
? 2011-2014 microchip technology inc. ds70000652f-page 277 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 25.0 development support the pic ? microcontrollers (mcu) and dspic ? digital signal controllers (dsc) are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? x ide software ? compilers/assemblers/linkers - mplab xc compiler - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families ? simulators - mplab x sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers/programmers - mplab icd 3 - pickit? 3 ? device programmers - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits and starter kits ? third-party development tools 25.1 mplab x integrated development environment software the mplab x ide is a single, unified graphical user interface for microchip and third-party software, and hardware development tool that runs on windows ? , linux and mac os ? x. based on the netbeans ide, mplab x ide is an entirely new ide with a host of free software components and plug-ins for high- performance application development and debugging. moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. with complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, mplab x ide is flexible and friendly enough for new users. with the ability to support multiple tools on multiple projects with simultaneous debugging, mplab x ide is also suitable for the needs of experienced users. feature-rich editor: ? color syntax highlighting ? smart code completion makes suggestions and provides hints as you type ? automatic code formatting based on user-defined rules ? live parsing user-friendly, customizable interface: ? fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. ? call graph window project-based workspaces: ? multiple projects ? multiple tools ? multiple configurations ? simultaneous debugging sessions file history and bug tracking: ? local file history feature ? built-in support for bugzilla issue tracker
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 278 ? 2011-2014 microchip technology inc. 25.2 mplab xc compilers the mplab xc compilers are complete ansi c compilers for all of microchip?s 8, 16, and 32-bit mcu and dsc devices. these compilers provide powerful integration capabilities, superior code optimization and ease of use. mplab xc compilers run on windows, linux or mac os x. for easy source level debugging, the compilers provide debug information that is optimized to the mplab x ide. the free mplab xc compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. mplab xc compilers include an assembler, linker and utilities. the assembler generates relocatable object files that can then be archived or linked with other relo- catable object files and archives to create an execut- able file. mplab xc compiler uses the assembler to produce its object file. notable features of the assem- bler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command-line interface ? rich directive set ? flexible macro language ? mplab x ide compatibility 25.3 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code, and coff files for debugging. the mpasm assembler features include: ? integration into mplab x ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multipurpose source files ? directives that allow complete control over the assembly process 25.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 25.5 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic dsc devices. mplab xc compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command-line interface ? rich directive set ? flexible macro language ? mplab x ide compatibility
? 2011-2014 microchip technology inc. ds70000652f-page 279 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 25.6 mplab x sim software simulator the mplab x sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab x sim software simulator fully supports symbolic debugging using the mplab xc compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 25.7 mplab real ice in-circuit emulator system the mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs all 8, 16 and 32-bit mcu, and dsc devices with the easy-to-use, powerful graphical user interface of the mplab x ide. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (rj-11) or with the new high-speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab x ide. mplab real ice offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 25.8 mplab icd 3 in-circuit debugger system the mplab icd 3 in-circuit debugger system is microchip?s most cost-effective, high-speed hardware debugger/programmer for microchip flash dsc and mcu devices. it debugs and programs pic flash microcontrollers and dspic dscs with the powerful, yet easy-to-use graphical user interface of the mplab ide. the mplab icd 3 in-circuit debugger probe is connected to the design engineer?s pc using a high- speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 25.9 pickit 3 in-circuit debugger/ programmer the mplab pickit 3 allows debugging and program- ming of pic and dspic flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab ide. the mplab pickit 3 is connected to the design engineer?s pc using a full- speed usb interface and can be connected to the tar- get via a microchip debug (rj-11) connector (compati- ble with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to implement in-circuit debugging and in-circuit serial programming? (icsp?). 25.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages, and a mod- ular, detachable socket assembly to support various package types. the icsp cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an mmc card for file storage and data applications.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 280 ? 2011-2014 microchip technology inc. 25.11 demonstration/development boards, evaluation kits and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully functional systems. most boards include prototyping areas for adding custom circuitry and provide applica- tion firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demonstration/development board series of circuits, microchip has a line of evaluation kits and demonstra- tion software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. 25.12 third-party development tools microchip also offers a great collection of tools from third-party vendors. these tools are carefully selected to offer good value and unique functionality. ? device programmers and gang programmers from companies, such as softlog and ccs ? software tools from companies, such as gimpel and trace systems ? protocol analyzers from companies, such as saleae and total phase ? demonstration boards from companies, such as mikroelektronika, digilent ? and olimex ? embedded ethernet solutions from companies, such as ez web lynx, wiznet and iplogika ?
? 2011-2014 microchip technology inc. ds70000652f-page 281 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 26.0 electrical characteristics this section provides an overview of the dspic33f j16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family electrical characteristics. additional information will be pr ovided in future revisions of this document as it becomes available. absolute maximum ratings for the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. absolute maximum ratings ( 1 ) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss .......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant with respect to v ss ( 3 ) ..................................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd ? 3.0v ( 3 ) ................................................... -0.3v to +5.6v voltage on any 5v tolerant pin with respect to v ss when v dd ? 3.0v ( 3 ) ........................................ -0.3v to (v dd + 0.3v) maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ( 2 ) ...........................................................................................................................250 ma maximum output current sourced and sunk by any i/o pin excluding osco .........................................................1 5 ma maximum output current sourced and sunk by osco................................................................................ ............25 ma maximum current sunk by all ports .............................................................................................. .........................200 ma maximum current sourced by all ports ( 2 ) ...............................................................................................................200 ma note 1: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those, or any other conditions above those indicated in the operation listings of this specification, is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2: maximum allowable current is a function of the device maximum power dissipation (see tab l e 2 6- 2 ). 3: see the ?pin diagrams? section for 5v tolerant pins.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 282 ? 2011-2014 microchip technology inc. 26.1 dc characteristics table 26-1: operating mips vs. voltage characteristic v dd range (in volts) temp range (in c) max mips dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 dc5 v bor -3.6v ( 1 ) -40c to +85c 16 v bor -3.6v ( 1 ) -40c to +125c 16 note 1: overall functional device operation at v bor < v dd < v ddmin is ensured but not characterized. all device analog modules, such as the adc, etc., will function but with degraded performance below v ddmin . table 26-2: thermal operating conditions rating symbol min typ max unit industrial temperature devices operating junction temperature range t j -40 ? +125 c operating ambient temperature range t a -40 ? +85 c extended temperature devices operating junction temperature range t j -40 ? +140 c operating ambient temperature range t a -40 ? +125 c power dissipation: internal chip power dissipation: p int = v dd x (i dd ? ? i oh ) p d p int + pio w i/o pin power dissipation: i/o = ? ({v dd ? v oh } x i oh ) + ? (v ol x i ol ) maximum allowed power dissipation p dmax (t j ? t a )/ ? ja w table 26-3: thermal packaging characteristics characteristic symbol typ max unit notes package thermal resistance, 18-pin pdip ? ja 50 ? c/w 1 package thermal resistance, 20-pin pdip ? ja 50 ? c/w 1 package thermal resistance, 28-pin spdip ? ja 50 ? c/w 1 package thermal resistance, 18-pin soic ? ja 63 ? c/w 1 package thermal resistance, 20-pin soic ? ja 63 ? c/w 1 package thermal resistance, 28-pin soic ? ja 55 ? c/w 1 package thermal resistance, 20-pin ssop ? ja 90 ? c/w 1 package thermal resistance, 28-pin ssop ? ja 71 ? c/w 1 package thermal resistance, 28-pin qfn (6x6 mm) ? ja 37 ? c/w 1 package thermal resistance, 36-pin vtla (5x5 mm) ? ja 31.1 ? c/w 1 package thermal resistance, 44-pin tqfp ? ja 45 ? c/w 1 , 2 package thermal resistance, 44-pin qfn ? ja 32 ? c/w 1 , 2 package thermal resistance, 44-pin vtla ? ja 30 ? c/w 1 , 2 note 1: junction to ambient thermal resistance; theta- ja ( ? ja ) numbers are achieved by package simulations. 2: this package is available in dspic33fj32(gp/mc)104 devices only.
? 2011-2014 microchip technology inc. ds70000652f-page 283 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ ( 1 ) max units conditions operating voltage dc10 supply voltage ( 3 ) v dd ?v bor ? 3.6 v industrial and extended dc12 v dr ram data retention voltage ( 2 ) 1.8 ? ? v dc16 v por v dd start voltage to ensure internal power-on reset signal ?1.75v ss v dc17 s vdd v dd rise rate to ensure internal power-on reset signal 0.024 ? ? v/ms 0-2.4v in 0.1s note 1: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 2: this is the limit to which v dd may be lowered without losing ram data. 3: overall functional device operation at v bor < v dd < v ddmin is ensured but not characterized. all device analog modules, such as the adc, etc., will function but with degraded performance below v ddmin . table 26-5: electrical characteris tics: brown-out reset (bor) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min ( 1 ) typ max units conditions bo10 v bor bor event on v dd transition high-to-low 2.40 2.48 2.55 v see note 2 note 1: parameters are for design guidance only and are not tested in manufacturing. 2: overall functional device operation at v bor < v dd < v ddmin is ensured but not characterized. all device analog modules, such as the adc, etc., will function but with degraded performance below v ddmin .
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 284 ? 2011-2014 microchip technology inc. table 26-6: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typical ( 1 ) max units conditions operating current (i dd ) ( 2 ) ? dspic33fj16(gp/mc)10x devices dc20d 0.7 1.7 ma -40c 3.3v lprc (32.768 khz) ( 3 ) dc20a 0.7 1.7 ma +25c dc20b 1.0 1.7 ma +85c dc20c 1.3 1.7 ma +125c dc21d 1.9 2.6 ma -40c 3.3v 1 mips ( 3 ) dc21a 1.9 2.6 ma +25c dc21b 1.9 2.6 ma +85c dc21c 2.0 2.6 ma +125c dc22d 6.5 8.5 ma -40c 3.3v 4 mips ( 3 ) dc22a 6.5 8.5 ma +25c dc22b 6.5 8.5 ma +85c dc22c 6.5 8.5 ma +125c dc23d 12.2 16 ma -40c 3.3v 10 mips ( 3 ) dc23a 12.2 16 ma +25c dc23b 12.2 16 ma +85c dc23c 12.2 16 ma +125c dc24d 16 21 ma -40c 3.3v 16 mips dc24a 16 21 ma +25c dc24b 16 21 ma +85c dc24c 16 21 ma +125c note 1: data in ?typical? column is at 3.3v, +25c unless otherwise stated. 2: i dd is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements are as follows: ? oscillator is configured in ec mode, osc1 is driven with external square wave from rail-to-rail ? clko is configured as an i/o input pin in the configuration word ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled ? cpu, sram, program memory and data memory are operational ? no peripheral modules are operating; however, every peripheral is being clocked (pmdx bits are all zeroed) ? cpu executing while(1) statement 3: these parameters are characterized, but not tested in manufacturing.
? 2011-2014 microchip technology inc. ds70000652f-page 285 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 operating current (i dd ) ( 2 ) ? dspic33fj32(gp/mc)10x devices dc20d 1 2 ma -40c 3.3v lprc (32.768 khz) ( 3 ) dc20a 1 2 ma +25c dc20b 1.1 2 ma +85c dc20c 1.3 2 ma +125c dc21d 1.7 3 ma -40c 3.3v 1 mips ( 3 ) dc21a 2.3 ma +25c 3 dc21b 2.3 3 ma +85c dc21c 2.4 3 ma +125c dc22d 7 8.5 ma -40c 3.3v 4 mips ( 3 ) dc22a 7 8.5 ma +25c dc22b 7 ma +85c 8.5 8.5 dc22c 7 ma +125c dc23d 13.2 17 ma -40c 3.3v 10 mips ( 3 ) dc23a 13.2 17 ma +25c dc23b 13.2 17 ma +85c dc23c 13.2 17 ma +125c dc24d 17 22 ma -40c 3.3v 16 mips dc24a 17 ma +25c 22 dc24b 17 22 ma +85c dc24c 17 22 ma +125c table 26-6: dc characteristics: operating current (i dd ) (continued) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typical ( 1 ) max units conditions note 1: data in ?typical? column is at 3.3v, +25c unless otherwise stated. 2: i dd is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements are as follows: ? oscillator is configured in ec mode, osc1 is driven with external square wave from rail-to-rail ? clko is configured as an i/o input pin in the configuration word ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled ? cpu, sram, program memory and data memory are operational ? no peripheral modules are operating; however, every peripheral is being clocked (pmdx bits are all zeroed) ? cpu executing while(1) statement 3: these parameters are characterized, but not tested in manufacturing.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 286 ? 2011-2014 microchip technology inc. table 26-7: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typical ( 1 ) max units conditions idle current (i idle ): core off, clock on base current ( 2 ) ? dspic33fj16(gp/mc)10x devices dc40d 0.4 1.0 ma -40c 3.3v lprc (32.768 khz) ( 3 ) dc40a 0.4 1.0 ma +25c dc40b 0.4 1.0 ma +85c dc40c 0.5 1.0 ma +125c dc41d 0.5 1.1 ma -40c 3.3v 1 mips ( 3 ) dc41a 0.5 1.1 ma +25c dc41b 0.5 1.1 ma +85c dc41c 0.8 1.1 ma +125c dc42d 0.9 1.6 ma -40c 3.3v 4 mips ( 3 ) dc42a 0.9 1.6 ma +25c dc42b 1.0 1.6 ma +85c dc42c 1.2 1.6 ma +125c dc43a 1.6 2.6 ma +25c 3.3v 10 mips ( 3 ) 2.6 dc43d 1.6 ma -40c dc43b 1.7 2.6 ma +85c dc43c 2 2.6 ma +125c dc44d 2.4 3.8 ma -40c 3.3v 16 mips ( 3 ) dc44a 2.4 3.8 ma +25c dc44b 2.6 3.8 ma +85c dc44c 2.9 3.8 ma +125c note 1: data in ?typical? column is at 3.3v, +25c unless otherwise stated. 2: base idle current is measured as follows: ? cpu core is off, oscillator is configured in ec mode, osc1 is driven with external square wave from rail-to-rail ? clko is configured as an i/o input pin in the configuration word ? external secondary oscillator (sosc) is disabled (i.e., sosco and sosci pins are configured as digital i/o inputs) ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled ? no peripheral modules are operating; however, every peripheral is being clocked (pmdx bits are all zeroed) 3: these parameters are characterized, but not tested in manufacturing.
? 2011-2014 microchip technology inc. ds70000652f-page 287 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 idle current (i idle ): core off, clock on base current ( 2 ) ? dspic33fj32(gp/mc)10x devices dc40d 0.4 1.0 ma -40c 3.3v lprc (32.768 khz) ( 3 ) dc40a 0.4 1.0 ma +25c dc40b 0.4 1.0 ma +85c dc40c 0.5 1.0 ma +125c dc41d 0.5 1.1 ma -40c 3.3v 1 mips ( 3 ) dc41a 0.5 1.1 ma +25c dc41b 0.5 1.1 ma +85c dc41c 0.8 1.1 ma +125c dc42d 0.9 1.6 ma -40c 3.3v 4 mips ( 3 ) dc42a 0.9 1.6 ma +25c dc42b 1.0 1.6 ma +85c dc42c 1.2 1.6 ma +125c dc43a 1.6 2.6 ma +25c 3.3v 10 mips ( 3 ) 1.6 2.6 dc43d ma -40c dc43b 1.7 2.6 ma +85c dc43c 2.0 2.6 ma +125c dc44d 2.4 3.8 ma -40c 3.3v 16 mips ( 3 ) dc44a 2.4 3.8 ma +25c dc44b 2.6 3.8 ma +85c dc44c 2.9 3.8 ma +125c table 26-7: dc characteristics: idle current (i idle ) (continued) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typical ( 1 ) max units conditions note 1: data in ?typical? column is at 3.3v, +25c unless otherwise stated. 2: base idle current is measured as follows: ? cpu core is off, oscillator is configured in ec mode, osc1 is driven with external square wave from rail-to-rail ? clko is configured as an i/o input pin in the configuration word ? external secondary oscillator (sosc) is disabled (i.e., sosco and sosci pins are configured as digital i/o inputs) ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled ? no peripheral modules are operating; however, every peripheral is being clocked (pmdx bits are all zeroed) 3: these parameters are characterized, but not tested in manufacturing.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 288 ? 2011-2014 microchip technology inc. table 26-8: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typical ( 1 ) max units conditions power-down current (i pd ) ( 2 ) ? dspic33fj16(gp/mc)10x devices dc60d 27 250 a -40c 3.3v base power-down current ( 3 , 4 ) dc60a 32 250 a +25c dc60b 43 250 a +85c dc60c 150 500 a +125c dc61d 420 600 a -40c 3.3v watchdog timer current: ? i wdt ( 3 , 5 ) dc61a 420 600 a +25c dc61b 530 750 a +85c dc61c 620 900 a +125c power-down current (i pd ) ( 2 ) ? dspic33fj32(gp/mc)10x devices dc60d 27 250 a -40c 3.3v base power-down current ( 3 , 4 ) dc60a 32 250 a +25c dc60b 43 250 a +85c dc60c 150 500 a +125c dc61d 420 600 a -40c 3.3v watchdog timer current: ? i wdt ( 3 , 5 ) dc61a 420 600 a +25c dc61b 530 750 a +85c dc61c 620 900 a +125c note 1: data in the typical column is at 3.3v, +25c unless otherwise stated. 2: i pd (sleep) current is measured as follows: ? cpu core is off, oscillator is configured in ec mode, osc1 is driven with external square wave from rail-to-rail ? clko is configured as an i/o input pin in the configuration word ? external secondary oscillator (sosc) is disabled (i.e., sosco and sosci pins are configured as digital i/o inputs) ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled ? all peripheral modules are disabled (pmdx bits are all ones) ? vregs bit (rcon<8>) = 1 (i.e., core regulator is set to stand-by while the device is in sleep mode) ? on applicable devices, rtcc is disabled, plus the vregs bit (rcon<8>) = 1 3: the ? current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: these currents are measured on the device containing the most memory in this family. 5: these parameters are characterized, but not tested in manufacturing.
? 2011-2014 microchip technology inc. ds70000652f-page 289 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-9: dc characteristics: doze current (i doze ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended parameter no. typical ( 1 ) max doze ratio ( 2 ) units conditions doze current (i doze ) ( 2 ) ? dspic33fj16(gp/mc)10x devices dc73a 13.2 17.2 1:2 ma -40c 3.3v 16 mips dc73f 4.7 6.2 1:64 ma dc73g 4.7 6.2 1:128 ma dc70a 13.2 17.2 1:2 ma +25c 3.3v 16 mips dc70f 4.7 6.2 1:64 ma dc70g 4.7 6.2 1:128 ma dc71a 13.2 17.2 1:2 ma +85c 3.3v 16 mips dc71f 4.7 6.2 1:64 ma dc71g 4.7 6.2 1:128 ma dc72a 13.2 17.2 1:2 ma +125c 3.3v 16 mips dc72f 4.7 6.2 1:64 ma dc72g 4.7 6.2 1:128 ma doze current (i doze ) ( 2 ) ? dspic33fj32(gp/mc)10x devices dc73a 13.2 17.2 1:2 ma -40c 3.3v 16 mips dc73f 4.7 6.2 1:64 ma dc73g 4.7 6.2 1:128 ma dc70a 13.2 17.2 1:2 ma +25c 3.3v 16 mips dc70f 4.7 6.2 1:64 ma dc70g 4.7 6.2 1:128 ma dc71a 13.2 17.2 1:2 ma +85c 3.3v 16 mips dc71f 4.7 6.2 1:64 ma dc71g 4.7 6.2 1:128 ma dc72a 13.2 17.2 1:2 ma +125c 3.3v 16 mips dc72f 4.7 6.2 1:64 ma dc72g 4.7 6.2 1:128 ma note 1: data in the typical column is at 3.3v, +25c unless otherwise stated. 2: i doze is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i doze measurements are as follows: ? oscillator is configured in ec mode, osc1 is driven with external square wave from rail-to-rail ? clko is configured as an i/o input pin in the configuration word ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled ? cpu, sram, program memory and data memory are operational ? no peripheral modules are operating; however, every peripheral is being clocked (pmdx bits are all zeros) ? cpu executing while(1) statement
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 290 ? 2011-2014 microchip technology inc. table 26-10: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ ( 1 ) max units conditions v il input low voltage di10 i/o pins v ss ?0.2v dd v di15 mclr v ss ?0.2v dd v di18 i/o pins with sdax, sclx v ss ?0.3 v dd v smbus disabled di19 i/o pins with sdax, sclx v ss ? 0.8 v smbus enabled v ih input high voltage di20 i/o pins not 5v tolerant ( 4 ) i/o pins 5v tolerant ( 4 ) 0.7 v dd 0.7 v dd ? ? v dd 5.5 v v di28 sdax, sclx 0.7 v dd ? 5.5 v smbus disabled di29 sdax, sclx 2.1 ? 5.5 v smbus enabled i cnpu cnx pull-up current di30 50 250 450 ? av dd = 3.3v, v pin = v ss i il input leakage current ( 2 , 3 ) di50 i/o pins 5v tolerant ( 4 ) ??2 ? av ss ? v pin ? v dd , pin at high-impedance di51 i/o pins not 5v tolerant ( 4 ) ??1 ? av ss ? v pin ? v dd , pin at high-impedance, -40c ? t a ? +85c di51a i/o pins not 5v tolerant ( 4 ) ??2 ? a shared with external reference pins, -40c ? t a ? +85c di51b i/o pins not 5v tolerant ( 4 ) ??3.5 ? av ss ? v pin ? v dd , pin at high-impedance, -40c ? t a ? +125c di51c i/o pins not 5v tolerant ( 4 ) ??8 ? a analog pins shared with external reference pins, -40c ? t a ? +125c di55 mclr ??2 ? av ss ?? v pin ?? v dd di56 osc1 ? ? 2 ? av ss ?? v pin ?? v dd , xt and hs modes note 1: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current can be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see the ? pin diagrams ? section for the 5v tolerant i/o pins. 5: v il source < (v ss ? 0.3). characterized but not tested. 6: non-5v tolerant pins, v ih source > (v dd + 0.3), 5v tolerant pins, v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any ?positive? input injection current from input sources > 5.5v. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins, not excluded under i icl or i ich conditions, are permitted provided the mathematical ?absolute instantaneous? sum of the input injection currents from all pins do not exceed the specified limit. characterized but not tested.
? 2011-2014 microchip technology inc. ds70000652f-page 291 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 i icl input low injection current di60a 0 -5 ( 5 , 8 ) ? ma all pins except v dd , v ss , av dd , av ss , mclr , v cap , sosci, sosco and rb14 i ich input high injection current di60b 0 ? +5 ( 6 , 7 , 8 ) ma all pins except v dd , v ss , av dd , av ss , mclr , v cap , sosci, sosco, rb14 and digital 5v tolerant designated pins ?? i ict total input injection current (sum of all i/o and control pins) di60c -20 ( 9 ) ?+20 ( 9 ) ma absolute instantaneous sum of all input injection currents from all i/o pins (| i icl + | i ich |) ? ?? i ict table 26-10: dc characteristics: i/o pi n input specifications (continued) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ ( 1 ) max units conditions note 1: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current can be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see the ? pin diagrams ? section for the 5v tolerant i/o pins. 5: v il source < (v ss ? 0.3). characterized but not tested. 6: non-5v tolerant pins, v ih source > (v dd + 0.3), 5v tolerant pins, v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any ?positive? input injection current from input sources > 5.5v. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins, not excluded under i icl or i ich conditions, are permitted provided the mathematical ?absolute instantaneous? sum of the input injection currents from all pins do not exceed the specified limit. characterized but not tested.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 292 ? 2011-2014 microchip technology inc. table 26-11: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ ( 1 ) max units conditions do10 v ol output low voltage i/o pins: 4x sink driver pins ? all pins excluding osco ??0.4v i ol ? 6 ma, v dd = 3.3v, see note 1 output low voltage i/o pins: 8x sink driver pins ? osco ??0.4v i ol ? 10 ma, v dd = 3.3v, see note 1 do20 v oh output high voltage i/o pins: 4x source driver pins ? all pins excluding osco 2.4 ? ? v i ol ? -6 ma, v dd = 3.3v, see note 1 output high voltage i/o pins: 8x source driver pins ? osco 2.4 ? ? v i ol ? -10 ma, v dd = 3.3v, see note 1 do20a v oh 1 output high voltage i/o pins: 4x source driver pins ? all pins excluding osco 1.5 ? ? v i oh ? -12 ma, v dd = 3.3v, see note 1 2.0 ? ? i oh ? -11 ma, v dd = 3.3v, see note 1 3.0 ? ? i oh ? -3 ma, v dd = 3.3v, see note 1 output high voltage i/o pins: 8x source driver pins ? osco 1.5 ? ? v i oh ? -16 ma, v dd = 3.3v, see note 1 2.0 ? ? i oh ? -12 ma, v dd = 3.3v, see note 1 3.0 ? ? i oh ? -4 ma, v dd = 3.3v, see note 1 note 1: data in ?typ? column is at 3.3v, +25c unless otherwise stated.
? 2011-2014 microchip technology inc. ds70000652f-page 293 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-13: internal voltag e regulator specifications table 26-12: dc characteristics: program memory dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 3 ) min typ ( 1 ) max units conditions program flash memory d130a e p cell endurance 10,000 ? ? e/w -40 ? c to +125 ? c d131 v pr v dd for read v min ?3.6 vv min = minimum operating voltage d132b v pew v dd for self-timed write v min ?3.6 vv min = minimum operating voltage d134 t retd characteristic retention 20 ? ? year provided no other specifications are violated d135 i ddp supply current during programming ?10?ma d137a t pe page erase time 20.1 ? 26.5 ms t pe = 168517 frc cycles, t a = +85c, see note 2 d137b t pe page erase time 19.5 ? 27.3 ms t pe = 168517 frc cycles, t a = +125c, see note 2 d138a t ww word write cycle time 47.4 ? 49.3 s t ww = 355 frc cycles, t a = +85c, see note 2 d138b t ww word write cycle time 47.4 ? 49.3 s t ww = 355 frc cycles, t a = +125c, see note 2 note 1: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 2: other conditions: frc = 7.37 mhz, tun<5:0> = b'011111 (for min), tun<5:0> = b'100000 (for max). this parameter depends on the frc accuracy (see table 26-18 ) and the value of the frc oscillator tuning register (see register 8-3 ). for complete details on calculating the minimum and maximum time, see section 5.3 ?programming operations? . 3: these parameters are ensured by design, but are not characterized or tested in manufacturing. dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristics min typ max units comments ?c efc external filter capacitor value ( 1 ) 4.7 10 ? f capacitor must be low series resistance (< 5 ohms) note 1: typical v cap voltage = 2.5v when v dd ? v ddmin .
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 294 ? 2011-2014 microchip technology inc. 26.2 ac characteristics and timing parameters this section defines dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family ac characteristics and timing parameters. table 26-14: temperature and vo ltage specifications ? ac figure 26-1: load conditions for device timing specifications table 26-15: capacitiv e loading requirements on output pins ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended operating voltage v dd range as described in section 26.1 ?dc characteristics? . param no. symbol characteristic min typ max units conditions do50 c osc 2 osc2/sosc2 pin ? ? 15 pf in ms and hs modes when external clock is used to drive osc1 do56 c io all i/o pins and osc2 ? ? 50 pf ec mode do58 c b sclx, sdax ? ? 400 pf in i 2 c? mode v dd /2 c l r l pin pin v ss v ss c l r l = 464 ? c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 ? for all pins except osc2 load condition 2 ? for osc2
? 2011-2014 microchip technology inc. ds70000652f-page 295 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 26-2: external clock timing q1 q2 q3 q4 osc1 clko q1 q2 q3 q4 os20 os25 os30 os30 os40 os41 os31 os31 table 26-16: external clo ck timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symb characteristic min typ ( 1 ) max units conditions os10 f in external clki frequency (external clocks allowed only in ec and ecpll modes) dc ? 32 mhz ec oscillator crystal frequency 3.0 10 31 ? ? ? 10 32 33 mhz mhz khz ms hs sosc os20 t osc t osc = 1/f osc 31.25 ? dc ns os25 t cy instruction cycle time ( 2 , 4 ) 62.5 ? dc ns os30 tosl, to s h external clock in (osc1) ( 5 ) high or low time 0.45 x t osc ??nsec os31 tosr, to s f external clock in (osc1) ( 5 ) rise or fall time ??20nsec os40 tckr clko rise time ( 3 , 5 ) ?610ns os41 tckf clko fall time ( 3 , 5 ) ?610ns os42 g m external oscillator transconductance ( 4 ) 14 16 18 ma/v v dd = 3.3v, t a = +25c note 1: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 2: instruction cycle period (t cy ) equals two times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type, under standard operating conditions, with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. 3: measurements are taken in ec mode. the clko signal is measured on the osc2 pin. 4: these parameters are characterized by similarity, but are tested in manufacturing at f in = 32 mhz only. 5: these parameters are characterized by similarity, but are not tested in manufacturing.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 296 ? 2011-2014 microchip technology inc. table 26-17: pll clock ti ming specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ ( 1 ) max units conditions os50 f plli pll voltage controlled oscillator (vco) input frequency range ( 2 ) 3.0 ? 8 mhz ecpll and mspll modes os51 f sys on-chip vco system frequency ( 3 ) 12 ? 32 mhz os52 t lock pll start-up time (lock time) ( 3 ) ?? 2ms os53 d clk clko stability (jitter) ( 3 ) -2 1 +2 % note 1: data in ?typ? column is at 3.3v, +25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: these parameters are characterized by similarity, but are tested in manufacturing at 7.7 mhz input only. 3: these parameters are characterized by similarity, but are not tested in manufacturing. this specification is based on clock cycle by clock cycle measurements. the effective jitter for individual time bases, or communi- cation clocks used by the user application, are derived fr om dividing the clko stability specification by the square root of ?n? (where ?n? is equal to f osc , divided by the peripheral data rate clock). for example, if f osc = 32 mhz and the spi bit rate is 5 mhz, the effective jitter of the spi clock is equal to: d clk 32 5 ----- - ------------- - 2% 2.53 ---------- 0 . 7 9 % == table 26-18: ac characteristics: internal fast rc (frc) accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. characteristic min typ max units conditions internal frc accuracy @ 7.37 mhz ( 1 ) f20a frc -2 0.25 +2 % -40c ? t a ?? -10c v dd 3.0-3.6v f20b frc -1 0.25 +1 % -10c ? t a ?? +85c v dd 3.0-3.6v f20c frc -5 0.25 +5 % +85c ? t a ?? +125c v dd 3.0-3.6v note 1: frequency is calibrated at +25c and 3.3v. tunx bits may be used to compensate for temperature drift. table 26-19: internal lo w-power rc (lprc) accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. characteristic min typ max units conditions lprc @ 32.768 khz ( 1 , 2 ) f21a lprc -30 10 +20 % -40c ? t a ?? -10c v dd 3.0-3.6v f21b lprc -20 10 +30 % -10c ? t a ?? +85c v dd 3.0-3.6v f21c lprc -35 10 +35 % +85c ? t a ?? +125c v dd 3.0-3.6v note 1: change of lprc frequency as v dd changes. 2: lprc accuracy impacts the watchdog timer time-out period (t wdt 1). see section 23.4 ?watchdog timer (wdt)? for more information.
? 2011-2014 microchip technology inc. ds70000652f-page 297 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 26-3: clko and i/o ti ming characteristics note: refer to figure 26-1 for load conditions. i/o pin (input) i/o pin (output) di35 old value new value di40 do31 do32 table 26-20: i/o timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 2 ) min typ ( 1 ) max units conditions do31 t io r port output rise time ? 10 25 ns do32 t io f port output fall time ? 10 25 ns di35 t inp intx pin high or low time (input) 25 ? ? ns di40 t rbp cnx high or low time (input) 2 ? ? t cy note 1: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 2: these parameters are characterized, but are not tested in manufacturing.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 298 ? 2011-2014 microchip technology inc. figure 26-4: reset, watchdog timer, os cillator start-up timer and power-up timer timing characteristics v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset sy11 sy10 sy20 sy13 i/o pins sy13 note: refer to figure 26-1 for load conditions. fscm delay sy35 sy30 sy12 table 26-21: reset, watchdog timer, oscill ator start-up timer, power-up timer and brown-out reset timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symb characteristic ( 1 ) min typ ( 2 ) max units conditions sy10 t mc lmclr pulse width (low) 2 ? ? ? s sy11 t pwrt power-up timer period ? 64 ? ms sy12 t por power-on reset delay 3 10 30 ? s sy13 t ioz i/o high-impedance from mclr low or watchdog timer reset ??1.2 ? s sy20 t wdt 1 watchdog timer time-out period ? ? ? ms see section 23.4 ?watchdog timer (wdt)? and lprc parameter f21a ( table 26-19 ). sy30 t ost oscillator start-up time ? 1024 * t osc ??t osc = osc1 period sy35 t fscm fail-safe clock monitor delay ? 500 900 ? s note 1: these parameters are characterized but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated.
? 2011-2014 microchip technology inc. ds70000652f-page 299 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 26-5: timer1/2/3 external cl ock timing characteristics note: refer to figure 26-1 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck table 26-22: timer1 external clock timing requirements ( 1 ) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 2 ) min typ max units conditions ta10 t tx h t1ck high time synchronous mode greater of: 20 or (t cy + 20)/n ? ? ns must also meet parameter ta15 , n = prescale value (1, 8, 64, 256) asynchronous 35 ? ? ns ta11 t tx l t1ck low time synchronous mode greater of: 20 ns or (t cy + 20)/n ? ? ns must also meet parameter ta15 , n = prescale value (1, 8, 64, 256) asynchronous 10 ? ? ns ta15 t tx p t1ck input period synchronous mode greater of: 40 or (2 t cy + 40)/n ? ? ns n = prescale value (1, 8, 64, 256) os60 ft1 sosc1/t1ck oscillator input frequency range (oscillator enabled by setting the tcs (t1con<1>) bit) dc ? 50 khz ta20 t ckextmrl delay from external t1ck clock edge to timer increment 0.75 t cy + 40 ? 1.75 t cy + 40 ns note 1: timer1 is a type a. 2: these parameters are characterized by similarity, but are not tested in manufacturing.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 300 ? 2011-2014 microchip technology inc. table 26-23: timer2/4 external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ max units conditions tb10 ttxh txck high time synchronous mode greater of: 20 or (t cy + 20)/n ? ? ns must also meet parameter tb15 , n = prescale value (1, 8, 64, 256) tb11 ttxl txck low time synchronous mode greater of: 20 or (t cy + 20)/n ? ? ns must also meet parameter tb15 , n = prescale value (1, 8, 64, 256) tb15 ttxp txck input period synchronous mode greater of: 40 or (2 t cy + 40)/n ? ? ns n = prescale value (1, 8, 64, 256) tb20 t ckextmrl delay from external txck clock edge to timer increment 0.75 t cy + 40 ? 1.75 t cy + 40 ns note 1: these parameters are characterized, but are not tested in manufacturing. table 26-24: timer3/5 external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ max units conditions tc10 ttxh txck high time synchronous t cy + 20 ? ? ns must also meet parameter tc15 tc11 ttxl txck low time synchronous t cy + 20 ? ? ns must also meet parameter tc15 tc15 ttxp txck input period synchronous, with prescaler 2 t cy + 40 ? ? ns n = prescale value (1, 8, 64, 256) tc20 t ckextmrl delay from external txck clock edge to timer increment 0.75 t cy + 40 ? 1.75 t cy + 40 ns note 1: these parameters are characterized, but are not tested in manufacturing.
? 2011-2014 microchip technology inc. ds70000652f-page 301 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 26-6: input capture x (icx ) timing characteristics icx ic10 ic11 ic15 note: refer to figure 26-1 for load conditions. table 26-25: input capture x (icx) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min max units conditions ic10 tccl icx input low time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns ic11 tcch icx input high time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns ic15 tccp icx input period (t cy + 40)/n ? ns n = prescale value (1, 4, 16) note 1: these parameters are characterized by similarity, but are not tested in manufacturing.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 302 ? 2011-2014 microchip technology inc. figure 26-7: output compare x (ocx ) timing characteristics figure 26-8: ocx/pwmx module timing characteristics ocx oc11 oc10 (output compare note: refer to figure 26-1 for load conditions. or pwm mode) table 26-26: output compare x (o cx) module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ max units conditions oc10 tccf ocx output fall time ? ? ? ns see parameter do32 oc11 tccr ocx output rise time ? ? ? ns see parameter do31 note 1: these parameters are characterized by similarity, but are not tested in manufacturing. ocfa ocx active tri-state oc20 oc15 table 26-27: simple ocx/pwmx mode timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ max units conditions oc15 t fd fault input to pwmx i/o change ??t cy + 20 ns ns oc20 t flt fault input pulse width t cy + 20 ns ? ? ns note 1: these parameters are characterized by similarity, but are not tested in manufacturing.
? 2011-2014 microchip technology inc. ds70000652f-page 303 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 26-9: motor co ntrol pwmx module fault timi ng characteristics figure 26-10: motor cont rol pwmx module timing characteristics flta1 pwmx see note 1 note 1: for the logic state after a fault, refer to the faovxh:faovxl bits in the pxfltacon register. mp30 mp20 pwmx mp11 mp10 note: refer to figure 26-1 for load conditions. table 26-28: motor co ntrol pwmx module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ max units conditions mp10 t fpwm pwm output fall time ? ? ? ns see parameter do32 mp11 t rpwm pwm output rise time ? ? ? ns see parameter do31 mp20 t fd fault input ? to pwm i/o change ??50ns mp30 t fh minimum pulse width 50 ? ? ns note 1: these parameters are characterized by similarity, but are not tested in manufacturing.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 304 ? 2011-2014 microchip technology inc. table 26-29: spix maximum data/clock rat e summary for dspic33fj16(gp/mc)10x figure 26-11: spix master mode ( half-duplex, transmit only, cke = 0 ) timing characteristics for dspic33fj16(gp/mc)10x ac characteristics standard operating conditions: 2.4v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended maximum data rate master transmit only (half-duplex) master transmit/receive (full-duplex) slave transmit/receive (full-duplex) cke ckp smp 15 mhz table 26-30 ?? 0 , 10 , 10 , 1 10 mhz ? table 26-31 ? 10 , 11 10 mhz ? table 26-32 ? 00 , 11 15 mhz ? ? table 26-33 100 11 mhz ? ? table 26-34 110 15 mhz ? ? table 26-35 010 11 mhz ? ? table 26-36 000 sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 26-1 for load conditions.
? 2011-2014 microchip technology inc. ds70000652f-page 305 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 26-12: spix master mode ( half-duplex, transmit only, cke = 1 ) timing characteristics for dspic33fj16(gp/mc)10x table 26-30: spix master mode (half-duplex, transmit only) timing requirements for dspic33fj16(gp/mc)10x ac characteristics standard operating conditions: 2.4v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp10 tscp maximum sckx frequency ? ? 15 mhz see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdiv2sch, tdiv2scl sdox data output setup to first sckx edge 30 ? ? ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. therefore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 26-1 for load conditions. sp36 sp10
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 306 ? 2011-2014 microchip technology inc. figure 26-13: spix master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing characteristics for dspic33fj16(gp/mc)10x table 26-31: spix master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing requirements for dspic33fj16(gp/mc)10x ac characteristics standard operating conditions: 2.4v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp10 tscp maximum sckx frequency ? ? 10 mhz see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdov2sc, tdov2scl sdox data output setup to first sckx edge 30 ??ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ??ns sp41 tsch2dil, ts c l 2 d i l hold time of sdix data input to sckx edge 30 ??ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 100 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 26-1 for load conditions. sp36 sp41 lsb in bit 14 - - - -1 sdix sp40 sp10 msb in
? 2011-2014 microchip technology inc. ds70000652f-page 307 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 26-14: spix master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing characteristics for dspic33fj16(gp/mc)10x table 26-32: spix master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing requirements for dspic33fj16(gp/mc)10x ac characteristics standard operating conditions: 2.4v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp10 tscp maximum sckx frequency ? ? 10 mhz -40c to +125c, see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ??ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ??ns sp41 tsch2dil, ts c l 2 d i l hold time of sdix data input to sckx edge 30 ??ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 100 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 26-1 for load conditions.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 308 ? 2011-2014 microchip technology inc. figure 26-15: spix slave mo de (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing characteristics for dspic33fj16(gp/mc)10x ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp60 sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 26-1 for load conditions. sp50 sp35
? 2011-2014 microchip technology inc. ds70000652f-page 309 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-33: spix slave mo de (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing requirements for dspic33fj16(gp/mc)10x ac characteristics standard operating conditions: 2.4v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp70 tscp maximum sckx input frequency ? ? 15 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx input 120 ? ? ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 ? 50 ns see note 4 sp52 tsch2ssh tsc l2 s sh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge ??50ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 310 ? 2011-2014 microchip technology inc. figure 26-16: spix slave mo de (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing characteristics for dspic33fj16(gp/mc)10x ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp60 sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 26-1 for load conditions. sp50
? 2011-2014 microchip technology inc. ds70000652f-page 311 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-34: spix slave mo de (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing requirements for dspic33fj16(gp/mc)10x ac characteristics standard operating conditions: 2.4v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp70 tscp maximum sckx input frequency ? ? 11 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx input 120 ? ? ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 ? 50 ns see note 4 sp52 tsch2ssh tsc l2 s sh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge ??50ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 312 ? 2011-2014 microchip technology inc. figure 26-17: spix slave mode (full-duplex, cke = 0 , ckp = 1 , smp = 0 ) timing characteristics for dspic33fj16(gp/mc)10x ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 note: refer to figure 26-1 for load conditions. sdi x msb in
? 2011-2014 microchip technology inc. ds70000652f-page 313 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-35: spix slave mo de (full-duplex, cke = 0 , ckp = 1 , smp = 0 ) timing requirements for dspic33fj16(gp/mc)10x ac characteristics standard operating conditions: 2.4v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp70 tscp maximum sckx input frequency ? ? 15 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx input 120 ? ? ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 ? 50 ns see note 4 sp52 tsch2ssh tsc l2 s sh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 314 ? 2011-2014 microchip technology inc. figure 26-18: spix slave mo de (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing characteristics for dspic33fj16(gp/mc)10x ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 note: refer to figure 26-1 for load conditions. sdi x msb in
? 2011-2014 microchip technology inc. ds70000652f-page 315 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-36: spix slave mo de (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing requirements for dspic33fj16(gp/mc)10x ac characteristics standard operating conditions: 2.4v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp70 tscp maximum sckx input frequency ? ? 11 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx input 120 ? ? ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 ? 50 ns see note 4 sp52 tsch2ssh tsc l2 s sh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 316 ? 2011-2014 microchip technology inc. table 26-37: spix maximum data/clock rat e summary for dspic33fj32(gp/mc)10x figure 26-19: spix master mode ( half-duplex, transmit only, cke = 0 ) timing characteristics for dspic33fj32(gp/mc)10x ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended maximum data rate master transmit only (half-duplex) master transmit/receive (full-duplex) slave transmit/receive (full-duplex) cke ckp smp 15 mhz table 26-30 ?? 0 , 10 , 10 , 1 9 mhz ? table 26-31 ? 10 , 11 9 mhz ? table 26-32 ? 00 , 11 15 mhz ? ? table 26-33 100 11 mhz ? ? table 26-34 110 15 mhz ? ? table 26-35 010 11 mhz ? ? table 26-36 000 sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 26-1 for load conditions.
? 2011-2014 microchip technology inc. ds70000652f-page 317 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 26-20: spix master mode ( half-duplex, transmit only, cke = 1 ) timing characteristics for dspic33fj32(gp/mc)10x table 26-38: spix master mode (half-duple x, transmit only) timing requirements for dspic33fj32(gp/mc)10x ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp10 tscp maximum sckx frequency ? ? 15 mhz see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdiv2sch, tdiv2scl sdox data output setup to first sckx edge 30 ? ? ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. therefore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 26-1 for load conditions. sp36
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 318 ? 2011-2014 microchip technology inc. figure 26-21: spix master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing characteristics for dspic33fj32(gp/mc)10x table 26-39: spix master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing requirements for dspic33fj32(gp/mc)10x ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp10 tscp maximum sckx frequency ? ? 9 mhz see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdov2sc, tdov2scl sdox data output setup to first sckx edge 30 ??ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ??ns sp41 tsch2dil, ts c l 2 d i l hold time of sdix data input to sckx edge 30 ??ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 111 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 26-1 for load conditions. sp36 sp41 lsb in bit 14 - - - -1 sdix sp40 msb in
? 2011-2014 microchip technology inc. ds70000652f-page 319 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 figure 26-22: spix master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing characteristics for dspic33fj32(gp/mc)10x table 26-40: spix master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing requirements for dspic33fj32(gp/mc)10x ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp10 tscp maximum sckx frequency ? ? 9 mhz -40c to +125c, see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ??ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ??ns sp41 tsch2dil, ts c l 2 d i l hold time of sdix data input to sckx edge 30 ??ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 111 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 26-1 for load conditions.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 320 ? 2011-2014 microchip technology inc. figure 26-23: spix slave mo de (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing characteristics for dspic33fj32(gp/mc)10x ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp60 sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 26-1 for load conditions. sp50
? 2011-2014 microchip technology inc. ds70000652f-page 321 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-41: spix slave mo de (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing requirements for dspic33fj32(gp/mc)10x ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp70 tscp maximum sckx input frequency ? ? 15 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx input 120 ? ? ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 ? 50 ns see note 4 sp52 tsch2ssh tsc l2 s sh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge ??50ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 322 ? 2011-2014 microchip technology inc. figure 26-24: spix slave mo de (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing characteristics for dspic33fj32(gp/mc)10x ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 26-1 for load conditions. sp50
? 2011-2014 microchip technology inc. ds70000652f-page 323 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-42: spix slave mo de (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing requirements for dspic33fj32(gp/mc)10x ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp70 tscp maximum sckx input frequency ? ? 11 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx input 120 ? ? ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 ? 50 ns see note 4 sp52 tsch2ssh tsc l2 s sh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge ??50ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 324 ? 2011-2014 microchip technology inc. figure 26-25: spix slave mode (full-duplex, cke = 0 , ckp = 1 , smp = 0 ) timing characteristics for dspic33fj32(gp/mc)10x ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 note: refer to figure 26-1 for load conditions. sdi x msb in
? 2011-2014 microchip technology inc. ds70000652f-page 325 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-43: spix slave mo de (full-duplex, cke = 0 , ckp = 1 , smp = 0 ) timing requirements for dspic33fj32(gp/mc)10x ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp70 tscp maximum sckx input frequency ? ? 15 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ?w ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx input 120 ? ? ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 ? 50 ns see note 4 sp52 tsch2ssh tsc l2 s sh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 326 ? 2011-2014 microchip technology inc. figure 26-26: spix slave mo de (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing characteristics for dspic33fj32(gp/mc)10x ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 note: refer to figure 26-1 for load conditions. sdi x msb in
? 2011-2014 microchip technology inc. ds70000652f-page 327 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-44: spix slave mo de (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing requirements for dspic33fj32(gp/mc)10x ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic ( 1 ) min typ ( 2 ) max units conditions sp70 tscp maximum sckx input frequency ? ? 11 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns sp50 tssl2sch, tssl2scl ssx ? to sckx ? or sckx input 120 ? ? ns sp51 tssh2doz ssx ? to sdox output high-impedance 10 ? 50 ns see note 4 sp52 tsch2ssh tsc l2 s sh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, +25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefore, the sckx clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 328 ? 2011-2014 microchip technology inc. figure 26-27: i2cx bus start/stop bits ti ming characteristics (master mode) figure 26-28: i2cx bus data timing characteristics (master mode) sclx sdax start condition stop condition im30 note: refer to figure 26-1 for load conditions. im31 im33 im34 im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 sclx sdax in sdax out note: refer to figure 26-1 for load conditions.
? 2011-2014 microchip technology inc. ds70000652f-page 329 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-45: i2cx bus data timing requirements (master mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min ( 1 ) max units conditions im10 t lo : scl clock low time 100 khz mode t cy /2 (brg + 1) ? ? s 400 khz mode t cy /2 (brg + 1) ? ? s 1 mhz mode ( 2 ) t cy /2 (brg + 1) ? ? s im11 t hi : scl clock high time 100 khz mode t cy /2 (brg + 1) ? ? s 400 khz mode t cy /2 (brg + 1) ? ? s 1 mhz mode ( 2 ) t cy /2 (brg + 1) ? ? s im20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ( 2 ) ?100ns im21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ( 2 ) ?300ns im25 t su : dat data input setup time 100 khz mode 250 ? ns 400 khz mode 100 ? ns 1 mhz mode ( 2 ) 40 ? ns im26 t hd : dat data input hold time 100 khz mode 0 ? ? s 400 khz mode 0 0.9 ? s 1 mhz mode ( 2 ) 0.2 ? ? s im30 t su : sta start condition setup time 100 khz mode t cy /2 (brg + 1) ? ? s only relevant for repeated start condition 400 khz mode t cy /2 (brg + 1) ? ? s 1 mhz mode ( 2 ) t cy /2 (brg + 1) ? ? s im31 t hd : sta start condition hold time 100 khz mode t cy /2 (brg + 1) ? ? s after this period the first clock pulse is generated 400 khz mode t cy /2 (brg + 1) ? ? s 1 mhz mode ( 2 ) t cy /2 (brg + 1) ? ? s im33 t su : sto stop condition setup time 100 khz mode t cy /2 (brg + 1) ? ? s 400 khz mode t cy /2 (brg + 1) ? ? s 1 mhz mode ( 2 ) t cy /2 (brg + 1) ? ? s im34 t hd : sto stop condition hold time 100 khz mode t cy /2 (brg + 1) ? ns 400 khz mode t cy /2 (brg + 1) ? ns 1 mhz mode ( 2 ) t cy /2 (brg + 1) ? ns im40 t aa : scl output valid from clock 100 khz mode ? 3500 ns 400 khz mode ? 1000 ns 1 mhz mode ( 2 ) ?400ns im45 t bf : sda bus free time 100 khz mode 4.7 ? ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ? s 1 mhz mode ( 2 ) 0.5 ? ? s im50 c b bus capacitive loading ? 400 pf im51 t pgd pulse gobbler delay 65 390 ns see note 3 note 1: brg is the value of the i 2 c? baud rate generator. refer to ?inter-integrated circuit (i 2 c?)? (ds70195) in the ? dspic33/pic24 family reference manual?. please see the microchip web site for the latest ?dspic33/ pic24 family reference manual? sections. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 3: typical value for this parameter is 130 ns.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 330 ? 2011-2014 microchip technology inc. figure 26-29: i2cx bus start/stop bits timing characteristics (slave mode) figure 26-30: i2cx bus data timing characteristics (slave mode) sclx sdax start condition stop condition is34 is33 is31 is30 is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 sclx sdax in sdax out
? 2011-2014 microchip technology inc. ds70000652f-page 331 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-46: i2cx bus data timing requirements (slave mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. symbol characteristic min max units conditions is10 t lo : scl clock low time 100 khz mode 4.7 ? ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? ? s device must operate at a minimum of 10 mhz 1 mhz mode ( 1 ) 0.5 ? ? s is11 t hi : scl clock high time 100 khz mode 4.0 ? ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? ? s device must operate at a minimum of 10 mhz 1 mhz mode ( 1 ) 0.5 ? ? s is20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ( 1 ) ? 100 ns is21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ( 1 ) ? 300 ns is25 t su : dat data input setup time 100 khz mode 250 ? ns 400 khz mode 100 ? ns 1 mhz mode ( 1 ) 100 ? ns is26 t hd : dat data input hold time 100 khz mode 0 ? ? s 400 khz mode 0 0.9 ? s 1 mhz mode ( 1 ) 00.3 ? s is30 t su : sta start condition setup time 100 khz mode 4.7 ? ? s only relevant for repeated start condition 400 khz mode 0.6 ? ? s 1 mhz mode ( 1 ) 0.25 ? ? s is31 t hd : sta start condition hold time 100 khz mode 4.0 ? ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? ? s 1 mhz mode ( 1 ) 0.25 ? ? s is33 t su : sto stop condition setup time 100 khz mode 4.7 ? ? s 400 khz mode 0.6 ? ? s 1 mhz mode ( 1 ) 0.6 ? ? s is34 t hd : sto stop condition hold time 100 khz mode 4000 ? ns 400 khz mode 600 ? ns 1 mhz mode ( 1 ) 250 ns is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns 400 khz mode 0 1000 ns 1 mhz mode ( 1 ) 0 350 ns is45 t bf : sda bus free time 100 khz mode 4.7 ? ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ? s 1 mhz mode ( 1 ) 0.5 ? ? s is50 c b bus capacitive loading ? 400 pf note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only).
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 332 ? 2011-2014 microchip technology inc. table 26-47: adc module specifications ac characteristics standard operating conditions: 3.0v to 3.6v ( 6 ) (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ max. units conditions device supply ad01 av dd module v dd supply ( 2 , 4 ) greater of: v dd ? 0.3 or 2.9 ? lesser of: v dd + 0.3 or 3.6 v ad02 av ss module v ss supply ( 2 , 5 ) v ss ? 0.3 ? v ss + 0.3 v ad09 i ad operating current ? 7.0 9.0 ma see note 1 analog input ad12 v inh input voltage range v inh ( 2 ) v inl ?av dd v this voltage reflects s&h channels 0, 1, 2 and 3 (ch0-ch3), positive input ad13 v inl input voltage range v inl ( 2 ) av ss ?av ss + 1v v this voltage reflects s&h channels 0, 1, 2 and 3 (ch0-ch3), negative input ad17 r in recommended impedance of analog voltage source ( 3 ) ? ? 200 ? note 1: these parameters are not characterized or tested in manufacturing. 2: these parameters are characterized, but are not tested in manufacturing. 3: these parameters are assured by design, but are not characterized or tested in manufacturing. 4: this pin may not be available on all devices; in which case, this pin will be connected to v dd internally. see the ?pin diagrams? section for availability. 5: this pin may not be available on all devices; in which case, this pin will be connected to v ss internally. see the ?pin diagrams? section for availability. 6: overall functional device operation at v bor < v dd < v ddmin is ensured but not characterized. all device analog modules, such as the adc, etc., will function but with degraded performance below v ddmin .
? 2011-2014 microchip technology inc. ds70000652f-page 333 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-48: 10-bit adc module specifications ac characteristics standard operating conditions: 3.0v to 3.6v ( 4 ) (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ max. units conditions 10-bit adc accuracy ? measurements with av dd /av ss ( 3 ) ad20b nr resolution 10 data bits bits ad21b inl integral nonlinearity -1 ? +1 lsb v inl = av ss = 0v, av dd = 3.6v ad22b dnl differential nonlinearity >-1 ? <1 lsb v inl = av ss = 0v, av dd = 3.6v ad23b g err gain error 3 7 15 lsb v inl = av ss = 0v, av dd = 3.6v ad24b e off offset error 1.5 3 7 lsb v inl = av ss = 0v, av dd = 3.6v ad25b ? monotonicity ? ? ? ? guaranteed ( 1 ) dynamic performance (10-bit mode) ( 2 ) ad30b thd total harmonic distortion ? ? -64 db ad31b sinad signal to noise and distortion 57 58.5 ? db ad32b sfdr spurious free dynamic range 72 ? ? db ad33b f nyq input signal bandwidth ? ? 550 khz ad34b enob effective number of bits 9.16 9.4 ? bits note 1: the analog-to-digital conversion result never decreases with an increase in the input voltage and has no missing codes. 2: these parameters are characterized by similarity, but are not tested in manufacturing. 3: these parameters are characterized, but are tested at 20 ksps only. 4: overall functional device operation at v bor < v dd < v ddmin is guaranteed but not characterized. all device analog modules, such as the adc, etc., will function but with degraded performance below v ddmin
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 334 ? 2011-2014 microchip technology inc. figure 26-31: adc conversion timing characteristics (chps<1:0> = 01 , simsam = 0 , asam = 0 , ssrc<2:0> = 000 ) figure 26-32: adc conversion timing characteristics (chps<1:0> = 01 , simsam = 0 , asam = 1 , ssrc<2:0> = 111 , samc<4:0> = 00001 ) t samp set samp ad61 adclk instruction samp ad60 done adxif 1 2 3 4 5 6 8 5 6 7 1 ? software sets adxcon. samp to start sampling. 2 ? sampling starts after discharge period. t samp is described in ?analog-to-digital converter (adc)? 3 ? software clears adxcon. samp to start conversion. 4 ? sampling ends, conversion sequence starts. 5 ? convert bit 9. 8 ? one t ad for end of conversion. ad50 7 8 6 ? convert bit 8. 7 ? convert bit 0. execution (ds70183) in the ? dspic33/pic24 family reference manual ?. clear samp ad55 ad55 ? convert bit 9. 1 2 3 4 5 6 4 5 6 8 1 ? software sets adxcon. adon to start ad operation. 2 ? sampling starts after discharge period. t samp is described in 3 ? convert bit 9. 4 ? convert bit 8. 5 ? convert bit 0. 7 3 6 ? one t ad for end of conversion. 7 ? begin conversion of next channel. 8 ? sample for time specified by samc<4:0>. adclk instruction set adon execution samp t samp adxif done ad55 ad55 t samp ad55 ad50 ?analog-to-digital converter (adc)? (ds70183) in the ?dspic33/pic24 family reference manual? .
? 2011-2014 microchip technology inc. ds70000652f-page 335 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-49: 10-bit adc conver sion timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ ( 1 ) max. units conditions clock parameters ( 2 ) ad50 t ad adc clock period 76 ? ? ns ad51 t rc adc internal rc oscillator period ? 250 ? ns conversion rates ad55 t conv conversion time ? 12 t ad ?? ad56 f cnv throughput rate ? ? 1.1 msps ad57 t samp sample time 2.0 t ad ??? timing parameters ad60 t pcs conversion start from sample trigger ( 1 ) 2.0 t ad ? 3.0 t ad ? auto-convert trigger (ssrc<2:0> = 111 ) not selected ad61 t pss sample start from setting sample (samp) bit ( 1 ) 2.0 t ad ? 3.0 t ad ? ad62 t css conversion completion to sample start (asam = 1 ) ( 1 ) ?0.5 t ad ?? ad63 t dpu time to stabilize analog stage from adc off to adc on ( 1 ) ??20 ? s note 1: these parameters are characterized but not tested in manufacturing. 2: because the sample caps will eventually lose charge, clock rates below 10 khz may affect linearity performance, especially at elevated temperatures.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 336 ? 2011-2014 microchip technology inc. table 26-50: comparator timing specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ max. units conditions 300 t resp response time ( 1 , 2 ) ? 150 400 ns 301 t mc 2 ov comparator mode change to output valid ( 1 ) ??10 ? s 302 t on 2 ov comparator enabled to output valid ( 1 ) ??10s note 1: parameters are characterized but not tested. 2: response time is measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd . table 26-51: comparator module specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ max. units conditions d300 v ioff input offset voltage ( 1 ) -20 10 20 mv d301 v icm input common-mode voltage ( 1 ) 0?a vdd ? 1.5v v d302 cmrr common-mode rejection ratio ( 1 ) -54 ? ? db d305 i vref internal voltage reference ( 1 ) 1.116 1.24 1.364 v note 1: parameters are characterized but not tested. table 26-52: comparator voltage re ference settling time specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ max. units conditions vr310 t set settling time ( 1 ) ??10 ? s note 1: settling time measured while cvrr = 1 and the cvr<3:0> bits transition from ? 0000 ? to ? 1111 ?.
? 2011-2014 microchip technology inc. ds70000652f-page 337 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 26-53: comparator volt age reference specifications dc characteristics standard operating conditions:3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ max. units conditions vrd310 cv res resolution cv rsrc /24 ? cv rsrc /32 lsb vrd311 cvr aa absolute accuracy ? ? 0.5 lsb vrd312 cvr ur unit resistor value (r) ? 2k ? ? table 26-54: ctmu current source specifications dc characteristics standard operating conditions:3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ max. units conditions ctmu current source ctmui1 i out 1 base range ( 1 ) 320 550 980 na irng<1:0> bits (ctmuicon<9:8>) = 0b01 ctmui2 i out 2 10x range ( 1 ) 3.2 5.5 9.8 a irng<1:0> bits (ctmuicon<9:8>) = 0b10 ctmui3 i out 3 100x range ( 1 ) 32 55 98 a irng<1:0> bits (ctmuicon<9:8>) = 0b11 internal diode ctmufv1 v f forward voltage ( 2 ) ? 0.77 ? v irng<1:0> bits (ctmuicon<9:8>) = 0b11 @ +25c ctmufv2 v fvr forward voltage rate ( 2 ) ? -1.38 ? mv/oc irng<1:0> bits (ctmuicon<9:8>) = 0b11 note 1: nominal value at center point of current trim range (itrim<5:0> bits (ctmuicon<15:10>) = 0b000000 ). 2: adc module configured for conversion speed of 500 ksps. parameters are characterized but not tested in manufacturing.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 338 ? 2011-2014 microchip technology inc. figure 26-33: forward voltage versus temperature 0.700 0.750 0.800 0.850 forward voltage @ +25c v f = 0.77 forward voltage rate v fvr = -1.38 mv/c 0.500 0.550 0.600 0.650 0.700 0.750 0.800 0.850 0.900 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 forward voltage (v) temperature (c) v f @ i out = 55 a note: this graph is a statistical summary based on a limited number of samples and this dat a is characterized but not tested in manufacturing.
? 2011-2014 microchip technology inc. preliminary ds70000652f-page 339 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 27.0 high-temperature el ectrical characteristics this section provides an overview of dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 family electrical characteristics for devices operating in an ambient temperature range of -40c to +150c. the specifications between -40c to +150c are identical to those shown in section 26.0 ?electrical characteristics? for operation between -40c to +125c, with the exception of the parameters listed in this section. parameters in this section begin with an h, which denotes: high temperature. for example, parameter dc10 in section 26.0 ?electrical characteristics? is the industrial and extended temperature equivalent of hdc10. absolute maximum ratings for the dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 high- temperature devices are listed below. exposure to these maximum rating conditions for extended periods can affect device reliability. functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. absolute maximum ratings ( 1 ) ambient temperature under bias ( 3 ) .........................................................................................................-40c to +150c storage temperature ............................................................................................................ .................. -65c to +160c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant with respect to v ss ( 4 ) .................................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd < 3.0v ( 4 ) ....................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd ? 3.0v ( 4 ) .................................................... -0.3v to 5.6v maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ( 2 ) ...........................................................................................................................250 ma maximum junction temperature................................................................................................... .......................... +155c maximum current sourced/sunk by any 4x i/o pin ................................................................................. ...................4 ma maximum current sourced/sunk by any 8x i/o pin ................................................................................. ...................8 ma maximum current sunk by all ports combined .................................................................................... ....................80 ma maximum current sourced by all ports combined ( 2 ) ................................................................................................80 ma note 1: stresses above those listed under ?absolute maximum ratings? can cause permanent damage to the device. this is a stress rating only and functional operation of the device at those, or any other conditions above those indicated in the operation listings of this specification, is not implied. exposure to maximum rating conditions for extended periods can affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see tab l e 2 7- 2 ). 3: aec-q100 reliability testing for devices intended to operate at +150c is 1,000 hours. any design in which the total operating time from +125c to +150c will be greater than 1,000 hours is not warranted without prior written approval from microchip technology inc. 4: refer to the ? pin diagrams ? section for 5v tolerant pins.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 340 preliminary ? 2011-2014 microchip technology inc. 27.1 high-temperature dc characteristics table 27-1: operating mips vs. voltage table 27-2: thermal operating conditions table 27-3: dc characteristics: operating current (i dd )) characteristic v dd range (in volts) temperature range (in c) max mips dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 hdc5 v bor ? 3.6v ( 1 ) -40c to +150c 5 note 1: overall functional device operation at v bormin < v dd < v ddmin is tested but not characterized. all device analog modules, such as the adc, etc., may have degraded performances below v ddmin . rating symbol min typ max unit high temperature devices operating junction temperature range t j -40 ? +155 c operating ambient temperature range t a -40 ? +150 c power dissipation: internal chip power dissipation: p int = v dd x (i dd ? ? i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = ? ({v dd ? v oh } x i oh ) + ? (v ol x i ol ) maximum allowed power dissipation p dmax (t j ? t a )/ ? ja w dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature parameter no. typical max units conditions operating current (i dd ) ? dspic33fj16(gp/mc)10x devices dc20e 1.3 1.7 ma 3.3v lprc (32.768 khz) dc22e 7.0 8.5 ma 3.3v 5 mips
? 2011-2014 microchip technology inc. preliminary ds70000652f-page 341 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 table 27-4: dc characteristics: operating current (i dd )) table 27-5: dc characteristics: idle current (i idle )) table 27-6: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature parameter no. typical max units conditions operating current (i dd ) ? dspic33fj32(gp/mc)10x devices dc20e 1.3 2.0 ma 3.3v lprc (32.768 khz) dc22e 7.25 8.5 ma 3.3v 5 mips dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature parameter no. typical max units conditions idle current (i idle ) ? dspic33fj16(gp/mc)10x devices dc40e 0.5 1.0 ma 3.3v lprc (32.768 khz) dc22e 1.2 1.6 ma 3.3v 5 mips idle current (i idle ) ? dspic33fj32(gp/mc)10x devices dc40e 0.5 1.0 ma 3.3v lprc (32.768 khz) dc22e 1.4 1.8 ma 3.3v 5 mips dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature parameter no. typical ( 1 ) max units conditions power-down current (i pd ) ? dspic33fjxx(gp/mc)10x dc60e 500 1000 ? a 3.3v base power-down current dc61e 650 1000 ? a 3.3v watchdog timer current: ? i wdt note 1: data in the typical column is 3.3v unless otherwise stated.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 342 preliminary ? 2011-2014 microchip technology inc. table 27-7: dc characteristics: doze current (i doze ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +150c for high temperature parameter no. typical ( 1 ) max doze ratio units conditions doze current (i doze ) ? dspic33fj16(gp/mc)10x devices dc74a 4.3 7.2 1:2 ma 3.3v 5 mips dc74f 1.6 6.2 1:64 ma 3.3v 5 mips dc74g 1.5 6.2 1:128 ma 3.3v 5 mips doze current (i doze ) ? dspic33fj32(gp/mc)10x devices dc74a 4.7 7.2 1:2 ma 3.3v 5 mips dc74f 1.9 6.2 1:64 ma 3.3v 5 mips dc74g 1.4 6.2 1:128 ma 3.3v 5 mips note 1: data in the typical column is 3.3v unless otherwise stated. table 27-8: dc characteristics: program memory dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +150c for high temperature param no. symbol characteristic ( 1 ) min typ max units conditions program flash memory hd130 e p cell endurance 10,000 ? ? e/w -40 ? c to +150 ? c ( 2 ) hd134 t retd characteristic retention 20 ? ? year 1000 e/w cycles or less and no other specifications are violated note 1: these parameters are assured by design, but are not characterized or tested in manufacturing. 2: programming of the flash memory is allowed up to +150c. table 27-9: ac characteristics: internal fast rc (frc) accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) param no. characteristic min typ max units conditions internal frc accuracy @ 7.37 mhz ( 1 ) f20d frc -8 0.25 +8 % -40c ? t a ?? +150c v dd 3.0-3.6v note 1: frequency is calibrated at +25c and 3.3v. tunx bits may be used to compensate for temperature drift. table 27-10: internal lo w-power rc (lprc) accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) param no. characteristic min typ max units conditions lprc @ 32.768 khz ( 1 , 2 ) f21c lprc -40 10 +40 % -40c ? t a ?? +150c v dd 3.0-3.6v note 1: change of lprc frequency as v dd changes. 2: lprc accuracy impacts the watchdog timer time-out period (t wdt 1). see section 23.4 ?watchdog timer (wdt)? for more information.
? 2011-2014 microchip technology inc. ds70000652f-page 343 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 28.0 packaging information 28.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note: if the full microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 20-lead pdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example dspic33fj16mc 1330235 20-lead ssop xxxxxxxxxxx xxxxxxxxxxx yywwnnn example dspic33fj16 mc101-i/ss 1330235 101-e/p 20-lead soic xxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn example dspic33fj16 mc101-i/so 1310017 18-lead pdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example dspic33fj16gp 1330235 101-e/p 18-lead soic xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example dspic33fj16 gp101-e/so 1310017 3 e 3 e 3 e 3 e 3 e
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 344 ? 2011-2014 microchip technology inc. 28.1 package marking information (continued) example 33fj16mc 102/ml 1330235 28-lead ssop xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example 33fj16mc 102-e/ss 1330235 36-lead vtla xxxxxxxx xxxxxxxx yywwnnn example 33fj16mc 102/tl 1330235 28-lead spdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example dspic33fj16mc 1330235 28-lead soic xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example dspic33fj16mc 1330235 102-e/sp 102-e/so 28-lead qfn xxxxxxxx xxxxxxxx yywwnnn 3 e 3 e 3 e 3 e 3 e
? 2011-2014 microchip technology inc. ds70000652f-page 345 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 28.1 package marking information (continued) 44-lead vtla xxxxxxxx xxxxxxxx yywwnnn example 33fj32mc 104/tl 1330235 xxxxxxxxxx 44-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn dspic33fj example 32mc104 1330235 44-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example dspic33fj 32mc104 1330235 -e/pt 3 e 3 e 3 e -e/ml
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 346 ? 2011-2014 microchip technology inc. 28.2 package details

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? 2011-2014 microchip technology inc. ds70000652f-page 347 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 348 ? 2011-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011-2014 microchip technology inc. ds70000652f-page 349 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
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dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 352 ? 2011-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011-2014 microchip technology inc. ds70000652f-page 353 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
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? 2011-2014 microchip technology inc. ds70000652f-page 355 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 356 ? 2011-2014 microchip technology inc. 28-lead skinny plastic dual in-line (sp) ? 300 mil body [spdip] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 28 pitch e .100 bsc top to seating plane a C C .200 molded package thickness a2 .120 .135 .150 base to seating plane a1 .015 C C shoulder to shoulder width e .290 .310 .335 molded package width e1 .240 .285 .295 overall length d 1.345 1.365 1.400 tip to seating plane l .110 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .050 .070 lower lead width b .014 .018 .022 overall row spacing eb C C .430 note 1 n 12 d e1 eb c e l a2 e b b1 a1 a 3 microchip technology drawing c04-070b
? 2011-2014 microchip technology inc. ds70000652f-page 357 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 !
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? 2011-2014 microchip technology inc. ds70000652f-page 359 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 360 ? 2011-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011-2014 microchip technology inc. ds70000652f-page 361 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 362 ? 2011-2014 microchip technology inc.
? 2011-2014 microchip technology inc. ds70000652f-page 363 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104
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? 2011-2014 microchip technology inc. ds70000652f-page 371 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 372 ? 2011-2014 microchip technology inc.
? 2011-2014 microchip technology inc. ds70000652f-page 373 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 appendix a: revision history revision a (january 2011) this is the initial released version of the document. revision b (february 2011) all major changes are referenced by their respective section in table a-1 . in addition, minor text and formatting changes were incorporated throughout the document. table a-1: major section updates section name update description high-performance, ultra low cost 16-bit digital signal controllers pin diagram updates (see ?pin diagrams? ): ? 20-pin pdip/soic/ssop (dspic33fj16mc101): removed the fltb1 pin from pin 10 ? 28-pin spdip/soic/ssop (dspic33fj16mc102): relocated the fltb1 pin from pin 12 to pin 14; relocated the flta1 pin from pin 16 to pin 15 ? 28-pin qfn (dspic33fj16mc102): relocated the flta1 pin from pin 13 to pin 12; relocated the fltb1 pin from pin 9 to pin 11 ? 36-pin tla (dspic33fj16mc102): relocated the flta1 pin from pin 17 to pin 16; relocated the fltb1 pin from pin 10 to pin 15 section 1.0 ?device overview? added notes 1, 2, and 3 regarding the flta1 and fltb1 pins to the pinout i/o descriptions (see table 1-1). added section ?? . section 4.0 ?memory organization? updated all resets value for pxfltacon and pxfltabcon to the 6-output pwm1 register map (see table 4-9). added note 1 to the pmd register map (see table 4-29). section 6.0 ?resets? removed reset timing sequence information from section 6.2 ?system reset? , as this information is provided in figure 6-2. section 15.0 ?motor control pwm module? added note 2 and note 3 regarding the flta1 and fltb1 pins to the 6-channel pwm module block diagram (see figure 15-1). added section 15.2 ?pwm faults? and section 15.3 ?write- protected registers? . added note 2 and note 3 regarding the flta1 and fltb1 pins to the note boxes located below the pxfltacon and pxfltbcon registers (see register 15-9 and register 15-10). section 17.0 ?inter-integrated circuit? (i 2 c?)? updated the descriptions for the conditional if stren = 1 and if stren = 0 statements for the sclrel bit in the i2cx control register (see register 17-1). section 23.0 ?special features? added the rtsp effect column to the dspic33f configuration bits description (see table 23-3). section 26.0 ?electrical characteristics? added parameters 300 and d305 (see table 26-42 and table 26-43). section 27.0 ?packaging information? modified the pending tla packaging page.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 374 ? 2011-2014 microchip technology inc. revision c (june 2011) this revision includes the following global update: ? all jtag references have been removed all other major changes are referenced by their respective section in tab le a - 2 . in addition, minor text and formatting changes were incorporated throughout the document. table a-2: major section updates section name update description high-performance, ultra low cost 16-bit digital signal controllers the tms, tdi, tdo, and tck pin names were removed from these pin diagrams: ? 28-pin spdip/soic/ssop ? 28-pin qfn ? 36-pin tla section 1.0 ?device overview? updated the buffer type to digital for the cted1 and cted2 pins (see table 1-1). section 4.0 ?memory organization? updated the sfr address for ic2con, ic3buf, and ic3con in the input capture register map (see table 4-7). added the vregs bit to the rcon register in the system control register map (see table 4-27). section 6.0 ?resets? added the vregs bit to the rcon register (see register 6-1). section 8.0 ?oscillator configuration? updated the definition for cosc<2:0> = 001 and nosc<2:0> = 001 in the osccon register (see register 8-1). section 15.0 ?motor control pwm module? updated the title for example 15-1 to include a reference to the assembly language. added example 15-2, which provides a c code version of the write- protected register unlock and fault clearing sequence. section 19.0 ?10-bit analog-to-digital converter (adc)? updated the ch0 section and added note 2 in both adc block diagrams (see figure 19-1 and figure 19-2). updated the multiplexer values in the adc conversion clock period block diagram (see figure 19-3. added the 01110 bit definitions and updated the 01101 bit definitions for the ch0sb<4:0> and ch0sa<4:0> bits in the ad1chs0 register (see register 19-5). section 22.0 ?charge time measurement unit (ctmu)? removed section 22.1 ?measuring capacitance?, section 22.2 ?measuring time?, and section 22.3 ?pulse generation and delay? updated the key features. added the ctmu block diagram (see figure 22-1). updated the itrim<5:0> bit definitions and added note 1 to the ctmu current control register (see register 22-3).
? 2011-2014 microchip technology inc. ds70000652f-page 375 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 section 23.0 ?special features? updated bits 5 and 4 of fpor, modified note 2, and removed note 3 from the configuration shadow register map (see table 23-1). updated bit 14 of config1 and removed note 5 from the configuration flash words (see table 23-2). updated the pllken configuration bit description (see table 23-3). added note 3 to connections for the on-chip voltage regulator (see figure 23-1). section 26.0 ?electrical characteristics? updated the standard operating conditions to: 3.0v to 3.6v in all tables. removed the voltage on v cap with respect to v ss entry in absolute maximum ratings (1) . updated the v dd range (in volts) in operating mips vs. voltage (see table 26-1). removed parameter dc18 and updated the minimum value for parameter dc 10 in the dc temperature and voltage specifications (see table 26-4). updated the characteristic definition and the typical value for parameter bo10 in electrical characteristics: bor (see table 26-5). updated note 2 in the dc characteristics: operating current (i dd ) (see table 26-6). updated note 2 in the dc characteristics: idle current (i idle ) (see table 26-7). updated note 2 and parameters dc60c and dc61a-dc61d in the dc characteristics: power-down current (i pd ) (see table 26-8). updated note 2 in the dc characteristics: doze current (i doze ) (see table 26-9). added note 1 to the internal voltage regulator specifications (see table 26-13). updated the minimum and maximum values for parameter f20a and the typical value for parameter f20b in ac characteristics: internal fast rc (frc) accuracy (see table 26-18). updated the minimum, typical, and maximum values for parameter f21a and f21b in internal low-power rc (lprc) accuracy (see table 26-19). updated the minimum, typical, and maximum values for parameter d305 in the comparator module specifications (see table 26-43). added parameters ctmufv1 and ctmufv2 and updated note 1 and the conditions for all parameters in the ctmu current source specifications (see table 26-46). added forward voltage versus temperature (see figure 26-25). table a-2: major section updates (continued) section name update description
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 376 ? 2011-2014 microchip technology inc. revision d (april 2012) this revision includes updates in support of the following new devices: ? dspic33fj32gp101 ? dspic33fj32gp102 ? dspic33fj32gp104 ? dspic33fj32mc101 ? DSPIC33FJ32MC102 ? dspic33fj32mc104 also, where applicable, new sections were added to peripheral chapters that provide information and links to the related resources, as well as helpful tips. for examples, see section 18.1 ?uart helpful tips? and section 18.2 ?uart resources? . this revision includes text and formatting changes that were incorporated throughout the document. all other major changes are referenced by their respective section in tab l e a - 3 . table a-3: major section updates section name update description ?16-bit digital signal controllers (up to 32- kbyte flash and 2-kbyte sram)? the content on the first page of this section was extensively reworked to provide the reader with the key features and functionality of this device family in an ?at-a-glance? format. table 2: ?dspic33fj32(gp/mc)101/102/104 device features? was added, which provides a feature overview of the new devices. all pin diagrams were updated (see ?pin diagrams? ). section 1.0 ?device overview? updated the notes in the device family block diagram (see figure 1-1 ). updated the following pinout i/o descriptions ( ta b l e 1 - 1 ): ?anx ? cnx ?rax ? rcx ?c vrefin (formerly cv ref ) relocated 1.1 ?referenced sources? to the previous chapter (see ?referenced sources? ). section 2.0 ?guidelines for getting started with 16-bit digital signal controllers? updated the recommended minimum connection diagram (see figure 2-1 ). section 4.0 ?memory organization? updated the existing program memory map (see figure 4-1 ) and added the program memory map for dspic33fj16(gp/mc)101/102 devices (see figure 4-1 ). updated the existing data memory map (see figure 4-4 ) and added the data memory map for dspic33fj32(gp/mc)101/102/104 devices with 2-kbyte ram (see figure 4-5 ). the following special function register maps were updated or added: ? table 4-5: change notification register map for dspic33fj32(gp/mc)104 devices ? table 4-6: interrupt controller register map ? table 4-8: timers register map for dspic33fj32(gp/mc)10x devices ? table 4-15: adc1 register map for dspic33fjxx(gp/mc)101 devices ? table 4-17: adc1 register map for dspic33fj32(gp/mc)104 devices ? table 4-22: peripheral pin select input register map ? table 4-26: peripheral pin select output register map for dspic33fj32(gp/ mc)104 devices ? table 4-28: porta register map for dspic33fj32(gp/mc)101/102 devices ? table 4-29: porta register map for dspic33fj32(gp/mc)104 devices ? table 4-36: portc register map for dspic33fj32(gp/mc)104 devices ? table 4-39: pmd register map
? 2011-2014 microchip technology inc. ds70000652f-page 377 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 section 7.0 ?interrupt controller? updated the interrupt vectors (see tab l e 7 - 1 ). the following registers were updated or added: ? register 7-5: ifs0: interrupt flag status register 0 ? register 7-11: iec1: interrupt enable control register 1 ? register 7-21: ipc6: interrupt priority control register 6 section 9.0 ?power- saving features? updated 9.5 pmd control registers . section 10.0 ?i/o ports? updated table 10-1: selectable input sources (maps input to function) (1) . updated table 10-2: output selection for remappable pin (rpn) the following registers were updated or added: ? register 10-4: rpinr4: peripheral pin select input register 4 ? register 10-6: rpinr8: peripheral pin select input register 8 ? register 10-19: rpor8: peripheral pin select output register 8 ? register 10-20: rpor9: peripheral pin select output register 9 ? register 10-21: rpor10: peripheral pin select output register 10 ? register 10-22: rpor11: peripheral pin select output register 11 ? register 10-23: rpor12: peripheral pin select output register 12 section 12.0 ?timer2/3 and timer4/5? the features and operation information was extensively updated in support of timer4/5 (see section 12.1 ?32-bit operation? and section 12.2 ?16-bit operation? ). the block diagrams were updated in support of the new timers (see figure 12-1 , figure 12-2 , and figure 12-3 ). the following registers were added: ? register 12-3: t4con: timer4 control register(1) ? register 12-4: t5con: timer5 control register(1) section 15.0 ?motor control pwm module? updated table 15-1: internal pull-down resistors on pwm fault pins . note 2 was added to register 15-5: pwmxcon1: pwmx control register 1 (1) . section 19.0 ?10-bit analog-to-digital converter (adc)? the number of available input pins and channels were updated from six to 14. updated figure 19-1: adc1 block diagram for dspic33fjxx(gp/mc)101 devices . updated figure 19-2: adc1 block diagram for dspic33fjxx(gp/mc)102 devices . added figure 19-3: adc1 block diagram for dspic33fj32(gp/mc)104 devices . the following registers were updated: ? register 19-4: ad1chs123: adc1 input channel 1, 2, 3 select register ? register 19-5: ad1chs0: adc1 input channel 0 select register ? register 19-6: ad1cssl: adc1 input scan select register low (1,2,3) ? register 19-7: ad1pcfgl: adc1 port configuration register low (1,2,3) table a-3: major section updates (continued) section name update description
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 378 ? 2011-2014 microchip technology inc. section 26.0 ?electrical characteristics? updated the absolute maximum ratings. updated table 26-3: thermal packaging characteristics . updated table 26-6: dc characteristics: operating current (idd) . updated table 26-7: dc characteristics: idle current (iidle) . updated table 26-8: dc characteristics: power-down current (ipd) . updated table 26-9: dc characteristics: doze current (idoze) . updated table 26-10: dc characteristics: i/o pin input specifications . replaced all spi specifications and figures (see table 26-29 through table 26-44 and figure 26-11 through figure 26-26 ). section 28.0 ?packaging information? added the following package marking information and package drawings: ? 44-lead tqfp ? 44-lead qfn ? 44-lead vtla (referred to as tla in the package drawings) table a-3: major section updates (continued) section name update description
? 2011-2014 microchip technology inc. ds70000652f-page 379 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 revision e (september 2012) this revision includes updates to the values in section 26.0 ?electrical characteristics? and updated packaging diagrams in section 28.0 ?packaging information? . there are minor text edits throughout the document. revision f (january 2014) this revision adds the high-temperature electrical characteristics chapter and updated packaging diagrams in section 28.0 ?packaging information? . there are minor text edits throughout the document.
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 380 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 381 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 index a absolute maximum ratings .............................................. 281 ac characteristics ............................................................ 294 10-bit adc specifications......................................... 333 adc specifications ................................................... 332 internal fast rc (frc) accuracy ..................... 296, 342 internal low-power rc (lprc) accuracy ........ 296, 342 load conditions ........................................................ 294 pll clock.................................................................. 296 temperature and voltage specifications .................. 294 adc control registers ...................................................... 222 helpful tips ............................................................... 221 initialization ............................................................... 217 key features............................................................. 217 resources................................................................. 221 alternate interrupt vector table (aivt) .............................. 95 analog-to-digital converter (adc).................................... 217 arithmetic logic unit (alu)................................................. 43 b bit-reversed addressing .................................................... 76 example ...................................................................... 77 implementation ........................................................... 76 sequence table (16-entry)......................................... 77 block diagrams 16-bit timer1 module................................................ 165 6-channel pwm1 module......................................... 182 adc1 conversion clock period................................ 221 adc1 for dspic33fj32(gp/mc)104 devices .......... 220 adc1 for dspic33fjxx(gp/mc)101 devices.......... 218 adc1 for dspic33fjxx(gp/mc)102 devices.......... 219 comparator i/o operating modes............................. 231 comparator voltage reference ................................ 232 connections for on-chip voltage regulator............. 266 ctmu module........................................................... 256 digital filter interconnect .......................................... 233 dsp engine ................................................................ 44 dspic33fjxx(gp/mc)10x cpu core ....................... 38 dspic33fjxx(gp/mc)10x devices ........................... 28 i 2 c module ................................................................ 204 input capture x module............................................. 175 mclr pin connections............................................... 34 multiplexing of remappable output for rpn............. 144 oscillator system ...................................................... 125 output compare x module........................................ 177 real-time clock and calendar (rtcc) module....... 243 recommended minimum connection......................... 34 remappable mux input for u1rx............................ 142 reset system.............................................................. 87 shared port structure ............................................... 140 spix module.............................................................. 197 timer2 and timer4 (16-bit)....................................... 169 timer2/3 and timer4/5 (32-bit)................................. 168 timer3 and timer5 (16-bit)....................................... 169 uartx simplified...................................................... 211 user-programmable blanking function .................... 232 watchdog timer (wdt) ............................................ 267 brown-out reset (bor) .................................................... 266 c charge time measurement unit. see ctmu. clock switching ................................................................ 132 enabling.................................................................... 132 sequence ................................................................. 132 code examples assembly code for write-protected register unlock, fault clearing sequence ..................... 184 c code for write-protected register unlock, fault clearing sequence .................................. 184 port write/read ........................................................ 141 pwrsav instruction syntax .................................... 133 setting the rtcwren bit........................................ 244 comparator....................................................................... 231 control registers...................................................... 234 configuration bits ............................................................. 261 description................................................................ 263 cpu control registers........................................................ 40 data addressing overview............................................................. 37 dsp engine ................................................................ 43 adder/subtracter overflow and saturation............................. 45 barrel shifter....................................................... 47 data accumulators write back .................................................. 46 data accumulators and adder/subtracter .......... 45 multiplier ............................................................. 45 overview............................................................. 37 special mcu features ............................................... 38 cpu clocking system ...................................................... 126 clock selection......................................................... 126 clock sources .......................................................... 126 configuration bit values for clock selection ............ 127 pll configuration..................................................... 127 ctmu control registers...................................................... 257 customer change notification service............................. 387 customer notification service .......................................... 387 customer support............................................................. 387 d data address space........................................................... 52 memory map for dspic33fj16(gp/mc)101/102 devices, 1-kbyte ram ....................................... 53 memory map for dspic33fj32(gp/mc)101/102/104 devices, 2-kbyte ram ............................................ 54 near data space ........................................................ 52 organization and alignment ....................................... 52 sfr space ................................................................. 52 software stack ........................................................... 73 width .......................................................................... 52 x and y spaces.......................................................... 55
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 382 ? 2011-2014 microchip technology inc. dc characteristics ............................................................ 282 brown-out reset (bor) ............................................ 283 doze current (i doze ) ........................................ 289, 342 high temperature ..................................................... 340 i/o pin input specifications ....................................... 290 i/o pin output specifications .................................... 292 idle current (i idle ) ............................................ 286, 341 operating current (i dd )............................. 284, 340, 341 operating mips vs. voltage.............................. 282, 340 power-down current (i pd ) ................................ 288, 341 program memory ...................................................... 293 temperature and voltage specifications .................. 283 thermal operating conditions .......................... 282, 340 thermal packaging ................................................... 282 development support ....................................................... 277 assembler mpasm assembler........................................... 278 c compilers mplab xc........................................................ 278 demonstration/development boards ........................ 280 evaluation and starter kits ....................................... 280 mplab assembler, linker, librarian ........................ 278 mplab icd 3 in-circuit debugger system .............. 279 mplab pm3 device programmer ............................ 279 mplab real ice in-circuit emulator system......... 279 mplab x integrated development environment software....................................... 277 mplink object linker/mplib object librarian ........ 278 pickit 3 in-circuit debugger/programmer ................ 279 software simulator (mplab x sim) ......................... 279 third-party development tools ................................ 280 doze mode........................................................................ 134 dspic33fj16(gp/mc)101/102 device features............................................................ 2 dspic33fj32(gp/mc)101/102/104 device features............................................................ 3 e electrical characteristics................................................... 281 equations device operating frequency .................................... 126 flash programming time............................................ 84 maximum row write time .......................................... 84 minimum row write time ........................................... 84 ms with pll mode .................................................... 127 errata .................................................................................. 24 f flash program memory....................................................... 83 control registers ........................................................ 85 operations .................................................................. 84 programming algorithm .............................................. 84 rtsp operation.......................................................... 84 table instructions........................................................ 83 g getting started with 16-bit dscs........................................ 33 analog and digital pins configuration during icsp ........................................................ 36 connection requirements .......................................... 33 decoupling capacitors ................................................ 33 external oscillator pins ............................................... 35 icsp pins.................................................................... 35 master clear (mclr ) pin............................................ 34 oscillator value conditions on start-up ...................... 36 unused i/os ................................................................ 36 h high-temperature electrical characteristics .................... 339 i i/o ports............................................................................ 139 configuring analog port pins.................................... 141 open-drain configuration......................................... 141 parallel i/o (pio) ...................................................... 139 write/read timing .................................................... 141 i 2 c control registers ...................................................... 205 operating modes ...................................................... 203 registers .................................................................. 203 in-circuit debugger........................................................... 268 in-circuit serial programming (icsp)............................... 268 input capture .................................................................... 175 control register........................................................ 176 input change notification (icn)........................................ 141 instruction addressing modes ............................................ 73 file register instructions ............................................ 73 fundamental modes supported ................................. 74 mac instructions ........................................................ 74 mcu instructions ........................................................ 73 move and accumulator instructions............................ 74 other instructions ....................................................... 74 instruction set summary .......................................................... 269 overview................................................................... 272 symbols used in opcode descriptions .................... 270 instruction-based power-saving modes........................... 133 idle ............................................................................ 134 sleep ........................................................................ 133 internet address ............................................................... 387 interrupt controller.............................................................. 95 interrupt registers iecx.................................................................... 98 ifsx .................................................................... 98 intcon1............................................................ 98 intcon2............................................................ 98 inttreg............................................................ 98 ipcx.................................................................... 98 interrupt setup procedures....................................... 124 initialization....................................................... 124 interrupt disable ............................................... 124 interrupt service routine (isr) ........................ 124 trap service routine (tsr) ............................. 124 interrupt vectors ......................................................... 97 reset sequence ......................................................... 95 interrupt vector table (ivt) ................................................ 95 interrupts coincident with power save instructions ......... 134 l lprc oscillator use with wdt........................................................... 267 m memory organization ......................................................... 49 microchip internet web site.............................................. 387 modulo addressing ............................................................. 75 applicability................................................................. 76 operation example ..................................................... 75 start and end address ............................................... 75 w address register selection .................................... 75
? 2011-2014 microchip technology inc. ds70000652f-page 383 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 motor control pwm .......................................................... 181 6-channel pwm1 module......................................... 181 control registers ...................................................... 185 faults ........................................................................ 183 at reset ............................................................ 183 write-protected registers......................................... 183 o oscillator configuration control registers ...................................................... 128 output compare ............................................................... 177 control register ........................................................ 179 modes ....................................................................... 178 active-high one-shot ....................................... 178 active-low one-shot........................................ 178 continuous pulse.............................................. 178 delayed one-shot ............................................ 178 module disabled ............................................... 178 pwm with fault protection ............................... 178 pwm without fault protection .......................... 178 toggle ............................................................... 178 p packaging ......................................................................... 343 details ....................................................................... 346 marking ..................................................... 343, 344, 345 peripheral module disable (pmd) .................................... 134 peripheral pin select (pps) .............................................. 142 available pins ........................................................... 142 controlling................................................................. 142 controlling configuration changes ........................... 145 helpful tips ............................................................... 146 i/o resources ........................................................... 146 input mapping ........................................................... 142 input selection sources for remappable pin (rpn) .......................................................... 143 output mapping ........................................................ 144 output selection sources for remappable pin (rpn) .......................................................... 144 registers................................................................... 147 pin diagrams ........................................................................ 4 pinout i/o descriptions (table) ............................................ 29 porta register map............................................................... 70 power-saving features .................................................... 133 clock frequency and switching................................ 133 program address space ..................................................... 49 construction................................................................ 78 data access from program memory using table instructions ............................................... 80 data access from, address generation...................... 79 memory map dspic33fj16(gp/mc)101/102 devices ............. 49 dspic33fj32(gp/mc)101/102/104 devices ...... 50 psv operation ............................................................ 81 reading data using program space visibility............ 81 table read instructions tblrdh ............................................................. 80 tblrdl .............................................................. 80 program memory interrupt vector ........................................................... 51 organization................................................................ 51 reset vector ............................................................... 51 programmer?s model........................................................... 39 r real-time clock and calendar (rtcc) ........................... 243 register maps 6-output pwm1, dspic33fjxxmc10x devices ....... 61 adc1, dspic33fj32(gp/mc)104 devices ................ 65 adc1, dspic33fjxx(gp/mc)101 devices ............... 63 adc1, dspic33fjxx(gp/mc)102 devices ............... 64 change notification, dspic33fj32(gp/mc)104 devices............................................................... 58 change notification, dspic33fjxx(gp/mc)102 devices............................................................... 58 change notification, dspic33fjxxgp101 devices............................................................... 58 change notification, dspic33fjxxmc101 devices............................................................... 58 comparator................................................................. 67 configuration flash words dspic33fj16(gp/mc)10x devices ................. 262 dspic33fj32(gp/mc)10x devices ................. 262 configuration shadow registers .............................. 262 cpu core ................................................................... 56 ctmu ......................................................................... 66 i2c1 ............................................................................ 62 input capture.............................................................. 61 interrupt controller...................................................... 59 nvm............................................................................ 72 output compare ......................................................... 61 pad configuration...................................................... 66 pmd............................................................................ 72 porta, dspic33fj16(gp/mc)101/102 devices............................................................... 69 porta, dspic33fj32(gp/mc)101/102 devices............................................................... 69 porta, dspic33fj32(gp/mc)104 devices ............. 70 portb, dspic33fj16gp101 devices ...................... 70 portb, dspic33fj16mc101 devices ...................... 70 portb, dspic33fj32(gp/mc)102 and dspic33fj32(gp/mc)104 devices.................... 71 portb, dspic33fj32gp101 devices ...................... 71 portb, dspic33fj32mc101 devices ...................... 71 portb, dspic33fjxx(gp/mc)102 and dspic33fj16(gp/mc)102 devices.................... 70 portc, dspic33fj32(gp/mc)104 devices ............. 71 pps input ................................................................... 67 pps output, dspic33fj32(gp/mc)104 devices....... 69 pps output, dspic33fjxx(gp/mc)102 devices ...... 68 pps output, dspic33fjxxgp101 devices ............... 68 pps output, dspic33fjxxmc101 devices............... 68 real-time clock and calendar .................................. 66 spi1............................................................................ 62 system control ........................................................... 72 timers, dspic33fj16(gp/mc)10x devices .............. 60 timers, dspic33fj32(gp/mc)10x devices .............. 60 uart1........................................................................ 62 registers ad1chs0 (adc1 input channel 0 select)............... 227 ad1chs123 (adc1 input channel 1, 2, 3 select) ..................................... 226 ad1con1 (adc1 control 1) .................................... 222 ad1con2 (adc1 control 2) .................................... 224 ad1con3 (adc1 control 3) .................................... 225 ad1cssl (adc1 input scan select low) ............... 228 ad1pcfgl (adc1 port configuration low) ............ 229
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 384 ? 2011-2014 microchip technology inc. alcfgrpt (alarm configuration)............................ 248 alrmval (alarm minutes and seconds value, alrmptr bits = 00) ........................................ 254 alrmval (alarm month and day value, alrmptr bits = 10) ........................................ 252 alrmval (alarm weekday and hours value, alrmptr bits = 01) ........................................ 253 clkdiv (clock divisor)............................................. 130 cmstat (comparator status).................................. 234 cmxcon (comparator x control) ............................. 235 cmxfltr (comparator x filter control) ................... 241 cmxmskcon (comparator x mask gating control).................................................. 239 cmxmsksrc (comparator x mask source select) .................................................. 237 corcon (core control) ...................................... 42, 99 ctmucon1 (ctmu control 1) ................................ 257 ctmucon2 (ctmu control 2) ................................ 258 ctmuicon (ctmu current control) ....................... 259 cvrcon (comparator voltage reference control)............................................ 242 devid (device id) .................................................... 265 devrev (device revision) ...................................... 265 i2cxcon (i2cx control) ........................................... 205 i2cxmsk (i2cx slave mode address mask) ............ 209 i2cxstat (i2cx status) ........................................... 207 icxcon (input capture x control) ............................ 176 iec0 (interrupt enable control 0) ............................. 108 iec1 (interrupt enable control 1) ............................. 109 iec2 (interrupt enable control 2) ............................. 110 iec3 (interrupt enable control 3) ............................. 110 iec4 (interrupt enable control 4) ............................. 111 ifs0 (interrupt flag status 0) ................................... 103 ifs1 (interrupt flag status 1) ................................... 105 ifs2 (interrupt flag status 2) ................................... 106 ifs3 (interrupt flag status 3) ................................... 106 ifs4 (interrupt flag status 4) ................................... 107 intcon1 (interrupt control 1).................................. 100 intcon2 (interrupt control 2).................................. 102 inttreg (interrupt control and status)................... 123 ipc0 (interrupt priority control 0) ............................. 112 ipc1 (interrupt priority control 1) ............................. 113 ipc14 (interrupt priority control 14) ......................... 119 ipc15 (interrupt priority control 15) ......................... 120 ipc16 (interrupt priority control 16) ......................... 121 ipc19 (interrupt priority control 19) ......................... 122 ipc2 (interrupt priority control 2) ............................. 114 ipc3 (interrupt priority control 3) ............................. 115 ipc4 (interrupt priority control 4) ............................. 116 ipc5 (interrupt priority control 5) ............................. 117 ipc6 (interrupt priority control 6) ............................. 117 ipc7 (interrupt priority control 7) ............................. 118 ipc9 (interrupt priority control 9) ............................. 119 nvmcon (flash memory control) ............................. 85 nvmkey (nonvolatile memory key) .......................... 85 ocxcon (output compare x control) ..................... 179 osccon (oscillator control) ................................... 128 osctun (frc oscillator tuning) ............................ 131 padcfg1 (pad configuration control) .................... 247 pmd1 (peripheral module disable control 1) ........... 135 pmd2 (peripheral module disable control 2) ........... 136 pmd3 (peripheral module disable control 3)........... 137 pmd4 (peripheral module disable control 4)........... 137 pwmxcon1 (pwmx control 1)................................ 188 pwmxcon2 (pwmx control 2)................................ 189 pwmxkey (pwmx unlock) ...................................... 196 pxdc1 (pwmx duty cycle 1) ................................... 195 pxdc2 (pwmx duty cycle 2) ................................... 195 pxdc3 (pwmx duty cycle 3) ................................... 195 pxdtcon1 (pwmx dead-time control 1) .............. 190 pxdtcon2 (pwmx dead-time control 2) .............. 191 pxfltacon (pwmx fault a control)...................... 192 pxfltbcon (pwmx fault b control)...................... 193 pxovdcon (pwmx override control) .................... 194 pxsecmp (pwmx special event compare) ............ 187 pxtcon (pwmx time base control)....................... 185 pxtmr (pwmx timer count value)......................... 186 pxtper (pwmx time base period) ........................ 186 rcfgcal (rtcc calibration and configuration) ............................................ 245 rcon (reset control)................................................ 88 rpinr0 (peripheral pin select input 0).................... 147 rpinr1 (peripheral pin select input 1).................... 148 rpinr11 (peripheral pin select input 11)................ 153 rpinr18 (peripheral pin select input 18)................ 154 rpinr20 (peripheral pin select input 20)................ 155 rpinr21 (peripheral pin select input 21)................ 156 rpinr3 (peripheral pin select input 3).................... 149 rpinr4 (peripheral pin select input 4).................... 150 rpinr7 (peripheral pin select input 7).................... 151 rpinr8 (peripheral pin select input 8).................... 152 rpor0 (peripheral pin select output 0).................. 157 rpor1 (peripheral pin select output 1).................. 157 rpor10 (peripheral pin select output 10).............. 162 rpor11 (peripheral pin select output 11).............. 162 rpor12 (peripheral pin select output 12).............. 163 rpor2 (peripheral pin select output 2).................. 158 rpor3 (peripheral pin select output 3).................. 158 rpor4 (peripheral pin select output 4).................. 159 rpor5 (peripheral pin select output 5).................. 159 rpor6 (peripheral pin select output 6).................. 160 rpor7 (peripheral pin select output 7).................. 160 rpor8 (peripheral pin select output 8).................. 161 rpor9 (peripheral pin select output 9).................. 161 rtcval (rtcc minutes and seconds value, rtcptr bits = 00)........................................... 251 rtcval (rtcc month and day value, rtcptr bits = 10)........................................... 249 rtcval (rtcc weekdays and hours value, rtcptr bits = 01)........................................... 250 rtcval (rtcc year value, rtcptr bits = 11)........................................... 249 spixcon1 (spix control 1)...................................... 200 spixcon2 (spix control 2)...................................... 202 spixstat (spix status and control) ....................... 199 sr (cpu status)............................................... 40, 99 t1con (timer1 control) .......................................... 166 t2con (timer2 control) .......................................... 170 t3con (timer3 control) .......................................... 171 t4con (timer4 control) .......................................... 172 t5con (timer5 control) .......................................... 173 uxmode (uartx mode).......................................... 213 uxsta (uartx status and control)......................... 215
? 2011-2014 microchip technology inc. ds70000652f-page 385 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 resets................................................................................. 87 bor (brown-out reset) .............................................. 87 bor and power-up timer (pwrt)............................. 92 cm (configuration mismatch reset)........................... 87 configuration mismatch (cm) ..................................... 93 external (extr).......................................................... 93 illegal condition .......................................................... 93 illegal opcode ..................................................... 93 security......................................................... 93, 94 uninitialized w register................................ 93, 94 iopuwr (illegal condition reset).............................. 87 illegal opcode ..................................................... 87 security............................................................... 87 uninitialized w register...................................... 87 mclr (master clear pin)............................................ 87 oscillator delays ......................................................... 90 por (power-on reset) ............................................... 87 power-on reset (por) ............................................... 92 software reset instruction (swr) ........................... 93 swr (reset instruction)........................................... 87 system cold reset .......................................................... 90 warm reset ........................................................ 90 trap conflict................................................................ 93 trapr (trap conflict reset)...................................... 87 watchdog timer time-out (wdto) ............................ 93 wdto (watchdog timer reset)................................. 87 revision history ................................................................ 373 rtcc control registers ...................................................... 245 module registers ...................................................... 244 register mapping...................................................... 244 s serial peripheral interface (spi) ....................................... 197 control registers ...................................................... 199 helpful tips ............................................................... 198 resources................................................................. 198 software stack pointer, frame pointer call stack frame...................................................... 73 special features ............................................................... 261 code protection ........................................................ 261 flexible configuration ............................................... 261 in-circuit emulation................................................... 261 in-circuit serial programming (icsp) ....................... 261 watchdog timer (wdt) ............................................ 261 t timer1 ............................................................................... 165 control register ........................................................ 166 timer2/3 and timer4/5...................................................... 167 16-bit operation........................................................ 167 32-bit operation........................................................ 167 control registers ...................................................... 170 timing diagrams adc conversion characteri stics (chps<1:0> = 01, simsam = 0, asam = 0, ssrc<2:0> = 000) ........................................... 334 adc conversion characteri stics (chps<1:0> = 01, simsam = 0, asam = 1, ssrc<2:0> = 111, samc<4:0> = 00001) ....................................... 334 brown-out reset situations ........................................ 92 clko and i/o ........................................................... 297 external clock........................................................... 295 i2cx bus data (master mode) .................................. 328 i2cx bus data (slave mode) .................................... 330 i2cx bus start/stop bits (master mode)................... 328 i2cx bus start/stop bits (slave mode)..................... 330 input capture x (icx) ................................................ 301 motor control pwmx ................................................ 303 motor control pwmx fault ....................................... 303 ocx/pwmx............................................................... 302 output compare x (ocx).......................................... 302 output compare x operation ................................... 178 reset, watchdog timer, oscillator start-up timer and power-up timer ......................................... 298 spix master mode (full-duplex, cke = 0, ckp = x, smp = 1) for dspic33fj16(gp/mc)10x.......... 307 spix master mode (full-duplex, cke = 0, ckp = x, smp = 1) for dspic33fj32(gp/mc)10x.......... 319 spix master mode (full-duplex, cke = 1, ckp = x, smp = 1) for dspic33fj16(gp/mc)10x.......... 306 spix master mode (full-duplex, cke = 1, ckp = x, smp = 1) for dspic33fj32(gp/mc)10x.......... 318 spix master transmit mode (half-duplex, cke = 0) for dspic33fj16(gp/mc)10x .......................... 304 spix master transmit mode (half-duplex, cke = 0) for dspic33fj32(gp/mc)10x .......................... 316 spix master transmit mode (half-duplex, cke = 1) for dspic33fj16(gp/mc)10x .......................... 305 spix master transmit mode (half-duplex, cke = 1) for dspic33fj32(gp/mc)10x .......................... 317 spix slave mode (full-duplex, cke = 0, ckp = 0, smp = 0) for dspic33fj16(gp/mc)10x.......... 314 spix slave mode (full-duplex, cke = 0, ckp = 0, smp = 0) for dspic33fj32(gp/mc)10x.......... 326 spix slave mode (full-duplex, cke = 0, ckp = 1, smp = 0) for dspic33fj16(gp/mc)10x.......... 312 spix slave mode (full-duplex, cke = 0, ckp = 1, smp = 0) for dspic33fj32(gp/mc)10x.......... 324 spix slave mode (full-duplex, cke = 1, ckp = 0, smp = 0) for dspic33fj16(gp/mc)10x.......... 308 spix slave mode (full-duplex, cke = 1, ckp = 0, smp = 0) for dspic33fj32(gp/mc)10x.......... 320 spix slave mode (full-duplex, cke = 1, ckp = 1, smp = 0) for dspic33fj16(gp/mc)10x.......... 310 spix slave mode (full-duplex, cke = 1, ckp = 1, smp = 0) for dspic33fj32(gp/mc)10x.......... 322 system reset ............................................................. 91 timer1/2/3 external clock ........................................ 299 timing requirements 10-bit adc conversion ............................................ 335 capacitive loading on output pins .......................... 294 clko and i/o ........................................................... 297 external clock .......................................................... 295 i2cx bus data (master mode) .................................. 329 i2cx bus data (slave mode) .................................... 331 input capture x (icx) ................................................ 301 motor control pwmx ................................................ 303 output compare x (ocx).......................................... 302 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset ............. 298 simple ocx/pwmx mode......................................... 302 spix master mode (full-duplex, cke = 0, ckp = x, smp = 1) for dspic33fj16(gp/mc)10x.......... 307 spix master mode (full-duplex, cke = 0, ckp = x, smp = 1) for dspic33fj32(gp/mc)10x.......... 319 spix master mode (full-duplex, cke = 1, ckp = x, smp = 1) for dspic33fj16(gp/mc)10x.......... 306 spix master mode (full-duplex, cke = 1, ckp = x, smp = 1) for dspic33fj32(gp/mc)10x.......... 318
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 386 ? 2011-2014 microchip technology inc. spix master transmit mode (half-duplex) for dspic33fj16(gp/mc)10x .......................... 305 spix master transmit mode (half-duplex) for dspic33fj32(gp/mc)10x .......................... 317 spix slave mode (full-duplex, cke = 0, ckp = 0, smp = 0) for dspic33fj16(gp/mc)10x .......... 315 spix slave mode (full-duplex, cke = 0, ckp = 0, smp = 0) for dspic33fj32(gp/mc)10x .......... 327 spix slave mode (full-duplex, cke = 0, ckp = 1, smp = 0) for dspic33fj16(gp/mc)10x .......... 313 spix slave mode (full-duplex, cke = 0, ckp = 1, smp = 0) for dspic33fj32(gp/mc)10x .......... 325 spix slave mode (full-duplex, cke = 1, ckp = 0, smp = 0) for dspic33fj16(gp/mc)10x .......... 309 spix slave mode (full-duplex, cke = 1, ckp = 0, smp = 0) for dspic33fj32(gp/mc)10x .......... 321 spix slave mode (full-duplex, cke = 1, ckp = 1, smp = 0) for dspic33fj16(gp/mc)10x .......... 311 spix slave mode (full-duplex, cke = 1, ckp = 1, smp = 0) for dspic33fj32(gp/mc)10x .......... 323 timer1 external clock............................................... 299 timer2/4 external clock............................................ 300 timer3/5 external clock............................................ 300 timing specifications comparator module .................................................. 336 comparator timing ................................................... 336 comparator voltage reference ................................ 337 comparator voltage reference settling time .......... 336 ctmu current source .............................................. 337 u uart control registers ...................................................... 213 helpful tips............................................................... 212 resources ................................................................ 212 universal asynchronous receiver transmitter (uart) .................................................. 211 using the rcon status bits............................................... 94 v voltage regulator (on-chip) ............................................ 266 w watchdog timer (wdt).................................................... 267 programming considerations ................................... 267 www address ................................................................. 387 www, on-line support ....... .............................................. 24
? 2011-2014 microchip technology inc. ds70000652f-page 387 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 388 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 389 dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . architecture: 33 = 16-bit digital signal controller flash memory family: fj = flash program memory, 3.3v product group: gp1 = general purpose family mc1 = motor control family pin count: 01 = 18-pin and 20-pin 02 = 28-pin and 32-pin temperature range: i = -40 ? c to +85 ? c (industrial) e=-40 ? c to +125 ? c (extended) package: p = plastic dual in-line - 300 mil body (pdip) ss = plastic shrink small outline - 5.3 mm body (ssop) sp = skinny plastic dual in-line - 300 mil body (spdip) so = plastic small outline - wide - 7.50 mil body (soic) ml = plastic quad, no lead - (28-pin) 6x6 mm body (qfn) pt = plastic thin quad flatpack - (44-pin) 10x10 mm body (tqfp) tl = very thin leadless array - (36-pin) 5x5 mm body (vtla) examples: a) dspic33fj16mc102-e/sp: motor control dspic33, 16-kbyte program memory, 28-pin, extended temperature, spdip package. microchip trademark architecture flash memory family program memory size (kbyte) product group pin count temperature range package pattern dspic 33 fj 1 6 m c 1 0 2 t e / sp - xxx tape and reel flag (if applicable)
dspic33fj16(gp/mc)101/102 and dspic33fj32(gp/mc)101/102/104 ds70000652f-page 390 ? 2011-2014 microchip technology inc. notes:
? 2011-2014 microchip technology inc. ds70000652f-page 391 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2011-2014, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62077-845-6 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification contai ned in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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